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參數(shù)資料
| 型號(hào)： | TC74AC166P_07 |
| 廠商： | Toshiba Corporation |
| 英文描述： | CMOS Digital Integrated Circuit Silicon Monolithic 8-Bit Shift Register (P-IN, S-OUT) |
| 中文描述： | CMOS數(shù)字集成電路硅單片8位移位寄存器（個(gè)P -，第S -輸出） |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 510K |
| 代理商： | TC74AC166P_07 |
TC74AC166P/F/FN
2007-10-01
6
Timing Requirements
(input: t
r
=
t
f
=
3 ns)
Test Condition
Ta
=
25°C
Ta
=
40 to
85°C
Characteristics
Symbol
V
CC
(V)
Limit
Limit
Unit
Minimum pulse width
(CK)
t
W (H)
t
W (L)
3.3
±
0.3
5.0
±
0.5
7.0
5.0
7.0
5.0
ns
Minimum pulse width
(CLR )
t
W (L)
3.3
±
0.3
5.0
±
0.5
8.0
5.0
8.0
5.0
ns
Minimum set-up time
(SI, PI)
t
s
3.3
±
0.3
5.0
±
0.5
8.0
4.0
8.0
4.0
ns
Minimum set-up time
(
L
S/ )
t
s
3.3
±
0.3
5.0
±
0.5
7.0
4.0
7.0
4.0
ns
Minimum hold time
(SI, PI)
t
h
3.3
±
0.3
5.0
±
0.5
0.5
0.5
0.5
0.5
ns
Minimum hold time
(
L
S/ )
t
h
3.3
±
0.3
5.0
±
0.5
1.0
1.0
1.0
1.0
ns
Minimum removal time
(
CLR
)
t
rem
3.3
±
0.3
5.0
±
0.5
4.0
1.5
4.0
1.5
ns
AC Characteristics
(C
L
=
50 pF, R
L
=
500
Ω
, input: t
r
=
t
f
=
3 ns)
Test Condition
Ta
=
25°C
Ta
=
40 to
85°C
Characteristics
Symbol
V
CC
(V)
Min
Typ.
Max
Min
Max
Unit
Propagation delay
time
(CK-QH)
t
pLH
t
pHL
3.3
±
0.3
5.0
±
0.5
9.4
6.6
16.1
10.0
1.0
1.0
18.3
11.4
ns
Propagation delay
time
(CLR -QH)
t
pHL
3.3
±
0.3
5.0
±
0.5
9.2
6.4
15.2
9.6
1.0
1.0
17.4
10.9
ns
Maximum clock
frequency
f
max
3.3
±
0.3
5.0
±
0.5
55
90
105
150
55
90
MHz
Input capacitance
C
IN
5
10
10
pF
Power dissipation
capacitance
C
PD
(Note)
67
pF
Note:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC
(opr)
=
C
PD
V
CC
f
IN
+
I
CC
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