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參數(shù)資料
| 型號： | TC74A7-50VCT |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Tiny Serial Digital Thermal Sensor |
| 中文描述： | 微型串行數(shù)字溫度傳感器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 430K |
| 代理商： | TC74A7-50VCT |
2002 Microchip Technology Inc.
DS21462B-page 7
TC74
3.0
DETAILED DESCRIPTION
3.1
Functional Description
The
information from its onboard solid-state sensor with a
resolution of ±1°C. It stores the data in an internal
register which is read through the serial port. The
system interface is a slave SMBus. The temperature
data can be read at any time through the SMBus port.
Eight SMBus addresses are programmable for the
TC74, which allows for a multi-sensor configuration.
Also, there is
low power Standby
temperature acquisition is suspended.
TC74
acquires
and
converts
temperature
mode
when
3.1.1
STANDBY MODE
The TC74 allows the host to put it into a low power (I
DD
= 5
μ
A, typical) Standby mode. In this mode, the A/D
converter is halted and the temperature data registers
are frozen. The SMBus port operates normally.
Standby mode is enabled by setting the SHDN bit in the
CONFIG register. Table 3-1 summarizes this operation.
TABLE 3-1:
STANDBY MODE OPERATION
3.1.2
SMBUS SLAVE ADDRESS
The TC74 is internally programmed to have a default
SMBus address value of 1001 101b. Seven other
addresses are available by custom order (contact
factory).
3.2
Serial Port Operation
The Serial Clock input (SCL) and bi-directional data
port (SDA) form a 2-wire bi-directional serial port for
programming
and
interrogating
following conventions are used in this bus architecture:
the
TC74.
The
TABLE 3-2:
SERIAL BUS CONVENTIONS
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TC74
always
operates as a Slave. The serial protocol is
illustrated in Figure 3-1 All data transfers have two
phases; all bytes are transferred MSB first. Accesses
are initiated by a START condition, followed by a device
address byte and one or more data bytes. The device
address byte includes a Read/Write selection bit. Each
access must be terminated by a STOP Condition. A
convention called
Acknowledge
(ACK) confirms receipt
of each byte. Note that SDA can change only during
periods when SCL is LOW (SDA changes while SCL is
HIGH are reserved for START and STOP Conditions).
SHDN Bit
Operating Mode
0
1
Normal
Standby
Term
Explanation
Transmitter
Receiver
Master
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers. (STOP)
The device addressed by the master.
A unique condition signaling the beginning of
a transfer indicated by SDA falling (High-Low)
while SCL is high.
A unique condition signaling the end of a
transfer indicated by SDA rising (Low-High)
while SCL is High.
A Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock
pulse for the ACK cycle.
Communication is not possible because the
bus is in use.
When the bus is idle, both SDA and SCL will
remain high.
The state of SDA must remain stable during
the High period of SCL in order for a data bit
to be considered valid. SDA only changes
state while SCL is low during normal data
transfers. (See START and STOP condi-
tions.)
Slave
START
STOP
ACK
Busy
NOT Busy
Data Valid
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