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參數(shù)資料
| 型號： | TC7109IJL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT HANDSHAKE 40CDIP |
| 標準包裝： | 10 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm） |
| 供應商設備封裝： | 40-Cerdip |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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2006 Microchip Technology Inc.
DS21456C-page 11
TC7109/A
FIGURE 3-3:
TC7109A RUN/HOLD Operation
3.2.4
DIRECT MODE
The data outputs (bits 1 through 8, low order bytes; bits
9 through 12, polarity and over range high order bytes)
are accessible under control of the byte and chip
enable terminals as inputs, with the MODE pin at a
LOW level. These three inputs are all active LOW.
Internal pull-up resistors are provided for an inactive
HIGH level when left open. When chip enable is LOW,
a byte enable input LOW will allow the outputs of the
byte to become active. A variety of parallel data
accessing techniques may be used, as shown in the
“Interfacing” section. (See Figure 3-4 and Table 3-1.)
The access of data should be synchronized with the
conversion cycle by monitoring the Status output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
FIGURE 3-4:
TC7109A Direct Mode
Output Timing
TABLE 3-1:
TC7109A DIRECT MODE
TIMING REQUIREMENTS
3.2.5
HANDSHAKE MODE
An alternative means of interfacing the TC7109A to
digital systems is provided when the Handshake Out-
put mode of the TC7109A becomes active in controlling
the flow of data, instead of passively responding to chip
and byte enable inputs. This mode allows a direct inter-
face between the TC7109A and industry standard
UARTs with no external logic required. The TC7109A
provides all the control and flag signals necessary to
sequence the two bytes of data into the UART and ini-
tiate their transmission in serial form when triggered
into the Handshake mode. The cost of designing
remote data acquisition stations is reduced using serial
data transmission to minimize the number of lines to
the central controlling processor.
Integrator Output
Internal Clock
Determinated at
Zero Crossing
Detection
Auto-Zero Phase I
Min 1790 Counts
Max 2041 Counts
Static in
Hold State
INT
Phase II
RUN/HOLD input is ignored until end of auto-zero phase.
*Note:
*
Internal Latch
Status Output
RUN/HOLD Input
7 Counts
= High-Impedance
CE/LOAD
As Input
tCEA
tBEA
HBEN
As Input
tDAB
LBEN
As Input
High Byte
Data
Low Byte
Data
Valid
tDAC
tDHC
Data
Valid
Data
Valid
Symbol
Description
Min
Typ
Max
Units
tBEA
Byte Enable Width
200
500
—
nsec
tDAB
Data Access Time
from Byte Enable
—
150
300
nsec
tDHB
Data Hold Time
from Byte Enable
—
150
300
nsec
tCEA
Chip Enable Width
300
500
nsec
tDAC
Data Access Time
from Chip Enable
—
200
400
nsec
tDHC
Data Hold Time
from Chip Enable
—
200
400
nsec
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