參數(shù)資料
型號： TC7107RIPL
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
封裝： REVERSE, PLASTIC, DIP-40
文件頁數(shù)： 25/26頁
文件大?。?/td> 623K
代理商： TC7107RIPL
TC7106/A/TC7107/A
DS21455B-page 8
2002 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
(All Pin designations refer to 40-Pin PDIP.)
3.1
Dual Slope Conversion Principles
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the
dual slope conversion technique will aid in following the
detailed operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
Input Signal Integration
Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (TSI). Time is measured by counting
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (TRI). See
Figure 3-1.
FIGURE 3-1:
BASIC DUAL SLOPE
CONVERTER
In a simple dual slope converter, a complete conver-
sion requires the integrator output to “ramp-up” and
“ramp-down.” A simple mathematical equation relates
the input signal, reference voltage and integration time.
EQUATION 3-1:
For a constant VIN:
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An inher-
ent benefit is noise immunity. Noise spikes are inte-
grated or averaged to zero during the integration
periods. Integrating ADCs are immune to the large con-
version errors that plague successive approximation
converters in high noise environments. Interfering sig-
nals with frequency components at multiples of the
averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set
to a multiple of the 50/60Hz power line period (see
Figure 3-2).
FIGURE 3-2:
NORMAL MODE
REJECTION OF DUAL
SLOPE CONVERTER
+
–
REF
Voltage
Analog
Input
Signal
+
–
DISPLAY
Switch
Driver
Control
Logic
Integrator
Output
Clock
Counter
Polarity Control
Phase
Control
VIN ≈ VREF
VIN ≈ 1/2 VREF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
C
Comparator
+/–
1
RC
VRTRI
RC
TSI
0
VIN(t)dt =
∫
Where:
VR = Reference voltage
TSI = Signal integration time (fixed)
TRI = Reference voltage integration time (variable).
VIN =VR
TRI
TSI
30
20
10
0
Normal
Mode
Rejection
(dB)
0.1/T
1/T
10/T
Input Frequency
T = Measured Period
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