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參數(shù)資料
| 型號： | TC55VBM316ATGN40 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 55 ns, PDSO48 |
| 封裝： | 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 209K |
| 代理商： | TC55VBM316ATGN40 |
TC55VBM316ATGN/ASGN40,55
2002-05-14
10/15
WRITE CYCLE 4 (
,
CONTROLLED)
(See Note 4)
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the
outputs will remain at high impedance.
(3)
If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
UB
LB
R/W
tWC
tAS
tWR
tWP
1
CE
VALID DATA IN
tDS
tDH
Hi-Z
tCW
CE2
tBW
tBE
tCOE
tODW
UB
, LB
tCW
(See Note 5)
Address
A0~A18 (Word Mode)
DOUT
I/O1~16 (Word Mode)
DIN
I/O1~16 (Word Mode)
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