參數(shù)資料
型號(hào): TC5565APL-15
廠商: Toshiba Corporation
英文描述: 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology
中文描述: 65,536位靜態(tài)隨機(jī)存取存儲(chǔ)器,可存儲(chǔ)8位為8192字利用CMOS技術(shù)
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 119K
代理商: TC5565APL-15
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
Note 1. R/W is High for Read Cycle.
2.
Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs
remain in a high impedance state.
3.
Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs
remain in a high impedance state.
4.
Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period.
DATA RETENTION CHARACTERISTICS (
Ta=0~70
°C)
SYMBOL
PARAMETER
V
DH
Data Retention Supply Voltage
Stand by Supply Current
MIN.
2.0
-
-
0
tRC(1)
TYP.
-
-
-
-
-
MAX.
5.5
50
100
-
-
UNIT
V
VDD=3.0V
VDD=5.5V
I
DDS2
uA
t
CDR
t
R
Chip Deselection to Data Retention Mode
Recovery Mode
Note (1) : Read cycle Time.
\CE1
Controlled Data Retention Mode (2)
us
us
CE2 Controlled Data Retention Mode (4)
相關(guān)PDF資料
PDF描述
TC5565APL 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology
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