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參數(shù)資料
| 型號： | TC1320EUATR |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | MSOP-8 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 442K |
| 代理商： | TC1320EUATR |
TC1320
DS21386B-page 4
2002 Microchip Technology Inc.
Serial Port AC Timing
fSMB
SMBus Clock Frequency
10
—
100
kHz
tIDLE
BusFreeTimePrior to New Transition
4.7
—
sec
tH(START)
START Condition Hold Time
4.0
—
sec
tSU(START)
START Condition Setup Time
4.7
—
sec
90% SCLto10% SDA
(for Repeated START
Condition)
tSU(STOP)
STOP Condition Setup Time
4.0
—
sec
tH-DATA
Data In Hold Time
100
—
nsec
tSU-DATA
Data In Setup Time
100
—
nsec
tLOW
Low Clock Period
4.7
—
sec
10% to 10%
tHIGH
High Clock Period
4
—
sec
90% to 90%
tF
SMBus Fall Time
—
300
nsec
90% to 10%
tR
SMBus Rise Time
—
1000
nsec
10% to 90%
tPOR
Power-on Reset Delay
—
500
—
sec
VDD ≥ VPOR (Rising Edge)
TC1320 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C ≤ TA ≤ +85°C, VREF = 1.2V unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Note
1:
SDA and SCL must be connected to VDD or GND.
2:
Measured at VOUT ≥ 50mV referred to GND to avoid output buffer clipping.
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