參數(shù)資料
型號(hào): TC1043CEQR
廠商: Microchip Technology Inc.
英文描述: Linear Building Block . Low Power Voltage Reference with Dual Op Amp, Dual Comparator, and Shutdown Mode
中文描述: 線性積木。低功耗電壓參考與雙路運(yùn)算放大器,雙比較,和關(guān)斷模式
文件頁(yè)數(shù): 7/20頁(yè)
文件大小: 508K
代理商: TC1043CEQR
2002 Microchip Technology Inc.
DS21347B-page 7
TC1043
EQUATION 4-1:
4.
Choose the rising threshold voltage for V
SRC
(V
THR
).
Calculate R
B
as follows:
5.
EQUATION 4-2:
6.
Verify the threshold voltages with these formu-
las:
V
SRC
rising:
EQUATION 4-3:
V
SRC
falling:
EQUATION 4-4:
4.5
32.768kHz ‘Time Of Day Clock’
Crystal Controlled Oscillator
A very stable oscillator driver can be designed by using
a crystal resonator as the feedback element. Figure 4-
5 shows a typical application circuit using this tech-
nique to develop a clock driver for a Time-Of-Day
(TOD) clock chip. The value of R
A
and R
B
determines
the DC voltage level at which the comparator trips; in
this case one-half of V
DD
. The RC time constant of R
C
and C
A
should be set several times greater than the
crystal oscillator’s period, which will ensure a 50% duty
cycle by maintaining a DC voltage at the inverting com-
parator input equal to the absolute average of the out-
put signal.
4.6
Non-Retriggerable One Shot Multi-
vibrator
Using two comparators, a non-retriggerable, one shot
multi-vibrator can be designed using the circuit config-
uration of Figure 4-6. A key feature of this design is that
the pulse width is independent of the magnitude of the
supply voltage because the charging voltage and the
intercept voltage are a fixed percentage of V
DD
. In addi-
tion, this one shot is capable of pulse width with as
much as a 99% duty cycle and exhibits input lockout to
ensure that the circuit will not re-trigger before the out-
put pulse has completely timed out. The trigger level is
the voltage required at the input to raise the voltage at
node A higher than the voltage at node B, and is set by
the resistive divider R4 and R10 and the impedance
network composed of R1, R2 and R3. When the one
shot has been triggered, the output of CMPTR2 is high,
causing the reference voltage at the non-inverting input
of CMPTR1 to go to V
. This prevents any additional
input pulses from disturbing the circuit until the output
pulse has timed out.
The value of the timing capacitor C1 must be small
enough to allow CMPTR1 to discharge C1 to a diode
voltage before the feedback signal from CMPTR2
(through R10) switches CMPTR1 to its high state and
allows C1 to start an exponential charge through R5.
Proper circuit action depends upon rapidly discharging
C1 through the voltage set by R6, R9 and D2 to a final
voltage of a small diode drop. Two propagation delays
after the voltage on C1 drops below the level on the
non-inverting input of CMPTR2, the output of CMPTR1
switches to the positive rail and begins to charge C1
through R5. The time delay which sets the output pulse
width results from C1 charging to the reference voltage
set by R6, R9 and D2, plus four comparator propaga-
tion delays. When the voltage across C1 charges
beyond the reference, the output pulse returns to
ground and the input is again ready to accept a trigger
signal.
4.7
Oscillators and Pulse Width
Modulators
Microchip’s linear building block comparators adapt
well to oscillator applications for low frequencies (less
than 100kHz). Figure 4-7 shows a symmetrical square
wave generator using a minimum number of compo-
nents. The output is set by the RC time constant of R4
and C1, and the total hysteresis of the loop is set by R1,
R2 and R3. The maximum frequency of the oscillator is
limited only by the large signal propagation delay of the
comparator in addition to any capacitive loading at the
output which degrades the slew rate.
To analyze this circuit, assume that the output is initially
high. For this to occur, the voltage at the inverting input
must be less than the voltage at the non-inverting input.
Therefore, capacitor C1 is discharged. The voltage at
the non-inverting input (V
H
) is:
EQUATION 4-5:
where, if R1 = R2 = R3, then:
EQUATION 4-6:
R
A
R
C
V
V
DD
----------
=
R
B
V
R
R
A
×
--------------------
R
A
--1
R
C
--1
---------V
=
V
THR
V
R
(
)
R
A
(
)
R
A
--1
R
B
--1
R
C
--1
+
+
=
V
THF
V
THR
R
-----------------------------
V
R
C
(
)
=
V
H
R2 V
R1
(
+
R3
R2
)
[
]
--------------------------------------------
=
V
H
2 V
3
)
-------------------
=
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