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參數(shù)資料
| 型號： | TB62600FG |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64BIT SHIFT REGISTER / LATCH DRIVER |
| 中文描述： | 64移位寄存器/鎖存驅動 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 504K |
| 代理商： | TB62600FG |
TB62600FG
2006-08-07
10
RECOMMENDED TIMING CONDITIONS
(Ta =
40~85°C, V
DD
= 4.5~5.5 V, V
SS
= 0 V)
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN
TYP.
MAX
UNIT
Clock Pulse Width
t
w CLK
―
50
―
―
ns
Enable Pulse Width
t
w EN
―
0.5
―
―
μs
Latch Pulse Width
t
w
LAT
―
50
―
―
ns
Clear Pulse Width
t
w CLR
―
80
―
―
ns
Data Set up Time
t
setup
―
37
50
―
ns
Data Hold Time
t
hold
―
50
―
―
ns
SWITCHING CHARACTERISTICS
(Ta = 25°C, V
DD
= 5 V, V
OUT
= 26 V, R
1
= 650
, C
L
= 15 pF)
CHARACTERISTIC
SYMBOL
TEST CONDITION
MIN
TYP.
MAX
UNIT
CLK
Outn
MMV
C / R = "L"
―
―
1000
R
Outn
MMV
C / R = "L"
―
―
1000
LAT1
Outn
MMV
C / R = "L"
―
―
1000
LAT2
Outn
MMV
C / R = "L"
―
―
1000
Propagation Delay Time
(Low
to
High)
EN
Outn
t
pLH
R = 750 k
, C = 2600 pF,Ta =
25°C
―
―
2500
ns
CLK
Outn
MMV
C / R = "L"
―
―
1000
LAT1
Outn
MMV
C / R = "L"
―
―
1000
LAT2
Outn
MMV
C / R = "L"
―
―
1000
Propagation Delay Time
(High
to
Low)
EN
n
Out
t
pHL
R = 750 k
, C = 2600 pF,Ta =
25°C
―
―
2500
ns
CLK
LATn
t
setup (L)
―
―
70
120
Set Up Time
CLK
S
IN
t
setup (D)
―
―
―
30
CLK
LATn
t
hold (L)
―
―
―
0
Hold Time
CLK
S
IN
t
hold (D)
―
―
―
20
ns
Clock Pulse Width
t
w CLK
―
―
―
50
ns
Latch Pulse Width
t
w
LATn
―
―
―
50
ns
Reset Pulse Width
t
w
R
―
―
―
50
ns
Enable Pulse Width
t
w EN
―
―
―
400
ns
Output Rise Time
t
or
OUTn
―
200
500
ns
Output Fall Time
t
of
OUTn
―
200
500
ns
Maximum Clock Frequency
f
MAX
Duty = 50%
10
15
―
Voltage Superviser Operating Pulse Width
t
w VS
V
DD
(H)
= 5 V, V
DD (L)
= 2 V
―
200
―
MMV Reset Time
t
MMV
R = 750 k
, C = 2600 pF,Ta =
25°C
1
3
5
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