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參數(shù)資料
| 型號： | TB28F016SC-110 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 2M X 8 FLASH 3.3V PROM, 110 ns, PDSO44 |
| 封裝： | 13.30 X 28.20 MM, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大小： | 725K |
| 代理商： | TB28F016SC-110 |
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E
BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
27
PRELIMINARY
SR.7 =
0
1
Start
Write 60H
Write D0H
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status
Register
V Range Error
1
0
Command Sequence
Error
SR.3 =
SR.5 =
SR.4,5 =
Clear Block Lock-Bits
Error
Bus
Operation
Command
Comments
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.5
1 = Clear Block Lock-Bits Error
Standby
Bus
Operation
Command
Comments
Write
Write
Clear Block
Lock-Bits Setup
Read
Data = 60H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
Status Register Data
Standby
Clear Block
Lock-Bits Confirm
Data = D0H
Addr = X
Clear Block Lock-Bits
Successful
Standby
0
1
Device Protect Error
SR.1=
Check SR.3
1 = V Error Detect
Check SR.1
1 = Device Protect Detect
RP# = V , Master Lock-Bit Is Set
IH
Figure 12. Clear Block Lock-Bits Flowchart
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