Writing of Input Mixers
SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com
Writing of input mixers must follow the guidelines on updating DAP coefficients.
The sequence for writing of input mixers, which are internal coefficients, is as follows:
1. Enable input mixer write. Write to register 0xF8: A5 A5 A5 A5 {4 bytes}.
2. Write to input mixer address register 0xF9: 00 00 00 ADDR {4 bytes} (where ADDR = 0x96, 0x99, 0xAA, or
0xA9).
3. Write the mixer value (3.23 format) to 0xFA: {zeros[37:0], mixer_value[25:0]} {total 8 bytes}.
The MSBs (38 bits) are zeros and LSBs (26 bits) comprise the mixer value in 3.23 format.
Sample Calculation for 3.23 Format
db
Linear
Decimal
Hex (3.23 Format)
0
1
8,388,608
0080 0000
5
1.7782794
14,917,288
00E3 9EA8
–5
0.5623413
4,717,260
0047 FACC
X
L = 10(X/20)
D = 8,388,608 × L
H = dec2hex (D, 8)
Table 2. Serial Control Interface Register Summary(1)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x28
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial-data interface
1
Description shown in subsequent section
0x05
register
0x05
System-control register 2
1
Description shown in subsequent section
0x40
0x06
Soft-mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0B
Channel 4 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0C
HP volume
1
Description shown in subsequent section
0x30 (0 dB)
0x0D
Channel-6 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0E
Volume configuration
1
Description shown in subsequent section
0x91
register
0x0F
1
Reserved(2)
0x10
Modulation-limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0x4C
0x12
IC delay channel 2
1
Description shown in subsequent section
0x34
0x13
IC delay channel 3
1
Description shown in subsequent section
0x1C
0x14
IC delay channel 4
1
Description shown in subsequent section
0x64
0x15
IC delay channel 5
1
Description shown in subsequent section
0xB0
0x16
IC delay channel 6
1
Description shown in subsequent section
0x90
0x17
Offset register
1
Reserved
0x00
0x18
1
Reserved(2)
(1)
(2)
Reserved registers should not be accessed.
40
Copyright 2009, Texas Instruments Incorporated