參數(shù)資料
型號(hào)： TAS5716PAP
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝： 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù)： 33/64頁(yè)
文件大?。?/td> 1398K
代理商： TAS5716PAP
www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009
1. Hold ALL logic inputs low. Power up AVDD/DVDD and wait for the inputs to settle in the allowed range.
2. Drive PDN = 1, MUTE = 1, and drive other logic inputs to the desired state.
3. Provide a stable MCLK, LRCLK, and SCLK (clock errors must be avoided during the initialization sequence) .
4. After completing step 3, wait 100
s, then drive RESET = 1, and wait 13.5 ms after RESET goes high.
5. Trim the internal oscillator (write 0x00 to register 0x1B).
6. Wait 50 ms while the part acquires lock.
7. Configure the DAP via I2C, e.g.:
–
Downmix control (0x21)
–
Biquads (0x23–0x24 and 0x29–0x38)
–
DRC parameters and controls (0x3A–0x46)
–
Bank select (0x50)
NOTE: User may not issue any I2C reads or writes to the above registers after this step is complete.
8. Configure remaining I2C registers, e.g.:
–
Shutdown group
–
De-emphasis
–
Input multiplexers
–
Output multiplexers
–
Channel delays
–
DC blocking
–
Hard/soft unmute from clock error
–
Serial data interface format
–
Clock register (manual clock mode only)
NOTE: The BKND_ERR register (0x1C) can only be written once with a value that is not reserved (00
and 01 are reserved values).
9. Exit all-channel shutdown (write 0 to bit 6 of register 0x05).
10. This completes the initialization sequence. From this step on, no further constraints are imposed on PDN,
MUTE, and clocks.
11. During normal operation the user may do the following:
a.
Write to the master or individual-channel volume registers.
b.
Write to the soft-mute register.
c.
Write to the clock and serial-data interface-format registers (in manual clock mode only).
d.
Write to bit 6 of register 0x05 to enter/exit all-channel shutdown. No other bits of register 0x05 may be
altered. After issuing the all-channel shutdown command, no further I2C transactions that address this
device are allowed for a period of at least: 1 ms + 1.3 × (period specified in start/stop register 0x1A) .
e.
PDN may be asserted (low) at any time. Once PDN is asserted, no I2C transactions that address this
device may be issued until PDN has been deasserted and the part has returned to active mode.
NOTE: When the device is in a power-down state (initiated via PDN), the part is not reset if RESET is
asserted.
NOTE: Once RESET is asserted, and as long as the part is in a reset state, the part does not power
down if PDN is asserted. For powering the part down, a negative edge on PDN must be issued when
RESET is high and the part is not in a reset state.
NOTE: No registers besides those explicitly listed in Steps a.–d. should be altered during normal
operation (i.e., after exiting all-channel shutdown).
NOTE: No registers should be read during normal operation (i.e., after exiting all-channel shutdown) .
12. To reconfigure registers:
a.
Return to all-channel shutdown (observe the shutdown wait time as specified in Step 11.d.).
b.
Drive PDN = 1, and hold MUTE stable.
c.
Provide a stable MCLK, LRCLK, and SCLK.
d.
Repeat configuration starting from step (6).
Copyright 2009, Texas Instruments Incorporated
39
Product Folder Link(s): TAS5716
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