參數(shù)資料
型號: TAS5708PHPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 20.2 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP48
封裝: 7 X 7 MM, GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 9/56頁
文件大?。?/td> 1104K
代理商: TAS5708PHPR
PWM Section
I
2C COMPATIBLE SERIAL CONTROL INTERFACE
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
www.ti.com ........................................................................................................................................................................................... SLOS570 – DECEMBER 2008
The TAS5708 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and
TAS570X GDE software development tool documentation. Also refer to GDE software development tool for
device data path.
The TAS5708 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
Copyright 2008, Texas Instruments Incorporated
17
Product Folder Link(s): TAS5708
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