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| 型號： | TAS5706PAPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64 |
| 封裝： | 10 X 10 MM, GREEN, PLASTIC, HTQFP-64 |
| 文件頁數(shù)： | 51/70頁 |
| 文件大小： | 1169K |
| 代理商： | TAS5706PAPRG4 |
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www.ti.com
SLOS550B – DECEMBER 2007 – REVISED DECEMBER 2010
OSCILLATOR TRIM REGISTER (0x1B)
The TAS5706 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. Currently, TI recommends a trim resistor value of 18.2 k
(1%).
This should be connected between OSC_RES and DVSS.
The factory-trim procedure simply enables the factory trim that was previously done at the factory.
Note that trim always must be run following reset of the device.
Oscillator Trim Enable Procedure Example
Write data 0x00 to register 0x1B (enable factory trim).
Table 18. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
–
Reserved (1)
–
0
–
Oscillator trim not done (read-only) (1)
–
1
–
Oscillator trim done (read only)
–
0
–
Reserved (1)
–
0
–
Select factory trim (Write a 0 to select factory trim; default is 1.)
–
1
–
Factory trim disabled (1)
–
0
Reserved (1)
(1)
Default values are in bold.
BKND_ERR REGISTER (0x1C)
When a back-end error signal is received (BKND_ERR = LOW), all the output stages are reset by setting all
PWM, VALID1, and VALID2 signals LOW. Subsequently, the modulator waits approximately for the time listed in
Table 19 before initiation of a reset.
Table 19. BKND_ERR Register (0x1C)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
–
0
Set back-end reset period to 0 ms (Reserved)
–
0
1
Set back-end reset period to 150 ms (Reserved)
–
0
1
0
Set back-end reset period to 299 ms (1)
–
0
1
Set back-end reset period to 449 ms
–
0
1
0
Set back-end reset period to 598 ms
–
0
1
0
1
Set back-end reset period to 748 ms
–
0
1
0
Set back-end reset period to 898 ms
–
0
1
Set back-end reset period to 1047 ms
–
1
0
Set back-end reset period to 1197 ms
–
1
0
1
Set back-end reset period to 1346 ms
–
1
0
1
0
Set back-end reset period to 1496 ms
–
1
0
1
Set back-end reset period to 1496 ms
–
1
–
Set back-end reset period to 1496 ms
(1)
Default values are in bold.
Copyright 2007–2010, Texas Instruments Incorporated
55
Product Folder Link(s): TAS5706
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