參數(shù)資料
型號： TAS5706PAPRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 20.6 W, 2 CHANNEL, AUDIO AMPLIFIER, PQFP64
封裝： 10 X 10 MM, GREEN, PLASTIC, HTQFP-64
文件頁數(shù)： 41/70頁
文件大小： 1169K
代理商： TAS5706PAPRG4
SLOS550B – DECEMBER 2007 – REVISED DECEMBER 2010
www.ti.com
Table 3. Serial Control Interface Register Summary (1) (continued)
NO. OF
INITIALIZATION
SUBADDRESS
REGISTER NAME
CONTENTS
BYTES
VALUE
0x3A
DRC1 ae
8
u[31:26], ae[25:0]
0x0080 0000
DRC1 (1 – ae)
u[31:26], (1 – ae)[25:0]
0x0000 0000
0x3B
DRC1 aa
8
u[31:26], aa[25:0]
0x0080 0000
DRC1 (1 – aa)
u[31:26], (1 – aa)[25:0]
0x0000 0000
0x3C
DRC1 ad
8
u[31:26], ad[25:0]
0x0080 0000
DRC1 (1 – ad)
u[31:26], (1 – ad)[25:0]
0x0000 0000
0x3D
DRC2 ae
8
u[31:26], ae[25:0]
0x0080 0000
DRC 2 (1 – ae)
u[31:26], (1 – ae)[25:0]
0x0000 0000
0x3E
DRC2 aa
8
u[31:26], aa[25:0]
0x0080 0000
DRC2 (1 – aa)
u[31:26], (1 – aa)[25:0]
0x0000 0000
0x3F
DRC2 ad
8
u[31:26], ad[25:0]
0x0080 0000
DRC2 (1 – ad)
u[31:26], (1 – ad)[27::0]
0x0000 0000
0x40
DRC1-T
4
T1[31:0]
0xFDA2 1490
0x41
DRC1-K
4
u[31:26], k1[25:0]
0x0384 2109
0x42
DRC1-O
4
u[31:24], O[23:16], O1[15:0]
0x0008 4210
0x43
DRC2-T
4
T2[31:0]
0xFDA2 1490
0x44
DRC2-K
4
u[31:24], k2'[22:0]
0x0384 2109
0x45
DRC2-O
4
u[31:24], O2[25:0]
0x0008 4210
0x46
DRC control
4
u[31:2], ch6[1], ch1_5[0]
0x0000 0000
0x47–0x49
4
Reserved(4)
0x0000 0000
0x50
4
Bank update command register
0x0000 0000
0x51–0xFF
4
Reserved(4)
0x0000 0000
(4)
Reserved registers should not be accessed.
CLOCK CONTROL REGISTER (0x00)
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks
are automatically determined by the TAS5706. In this case, the clock control register contains the auto-detected
clock status as automatically detected (D7–D2). Bits D7–D5 selects the sample rate. Bits D4–D2 select the
MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be
written to D0 to inform the DAP that the written clocks are valid.
Table 4. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
–
fS = 32-kHz sample rate
0
1
–
fS = 38-kHz sample rate
0
1
0
–
fS = 44.1-kHz sample rate
0
1
–
–
–
fS = 48-kHz sample rate
(1)
1
0
–
fS = 88.2-kHz sample rate
1
0
1
–
fS = 96-kHz sample rate
1
0
–
fS = 176.4-kHz sample rate
1
–
fS = 192-kHz sample rate
–
0
–
MCLK frequency = 64 × fS
(2)
–
0
1
–
MCLK frequency = 128 × fS
(3)
–
0
1
0
–
MCLK frequency = 192 × fS
(1)
Default values are in bold.
(2)
Rate not available for 32-, 44.1-, and 48-kHz data rates
(3)
Rate not available for 32-kHz data rate
46
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5706
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