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Overtemperature Protection
The TAS5186 has a two-level temperature-protection
system that asserts an active-low warning signal
(OTW) when the device junction temperature ex-
ceeds 125°C (typical), and If the device junction
temperature exceeds 155°C (typical), the device is
put into thermal shutdown, resulting in all half-bridge
outputs being set in the high-impedance state (Hi-Z)
and SD being asserted low.
UNDERVOLTAGE PROTECTION (UVP) AND
POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5186 fully
protect
the
device
in
any
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are
fully
GVDD_X and VDD supply voltages reach 10 V
(typical). Although GVDD_X and VDD are indepen-
dently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
when all supply voltages have increased above the
UVP threshold.
DEVICE RESET
When RESET is asserted low, the output FETs in all
half-bridges are forced into a high-impedance (Hi-Z)
state.
ACTIVE-BIAS CONTROL (ABC)
Audible
pop
noises
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorpor-
ating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
TAS5186
SLES136–MAY 2005
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capaci-
tor, to the desired potential before switching is started
on the PWM outputs. (For recommended configur-
ation, see the typical application schematic included
in this data sheet).
The start-up sequence can be controlled through
sequencing the M3 and RESET pins according to
Table 2
and
Table 3
.
Table 2. 5.1 Mode—All Output Channels Active
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
_B, _C
Hi-Z
COMMENT
_E, _F
Hi-Z
0
0
Hi-Z
All outputs dis-
abled, nothing is
switching.
OUT_BIAS en-
abled, all other
outputs disabled
OUT_BIAS dis-
abled, all other
outputs
switching
power-up/down
and
1
0
Active
Hi-Z
Hi-Z
operational
when
the
1
1
Hi-Z
Active
Active
Table 3. 2.1 Mode—Only Output Channels A, B,
and C Active
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
_B, _C
Hi-Z
COMMENT
_E, _F
Hi-Z
0
0
Hi-Z
All outputs dis-
abled, nothing is
switching.
OUT_BIAS en-
abled, all other
outputs disabled
OUT_BIAS dis-
abled, all other
outputs
switching
1
0
Active
Hi-Z
Hi-Z
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
is forced high.
0
1
Hi-Z
Active
Hi-Z
A rising-edge transition on the RESET input allows
the device to resume operation after an overload
fault.
When the TAS5186 is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
recommended.
are
often
associated
with
14