參數(shù)資料
型號(hào)： TAS5122DFD
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 音頻／視頻放大
英文描述： 37 W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO56
封裝： POWERPAD, PLASTIC, TSSOP-56
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 313K
代理商： TAS5122DFD
TAS5122
SLES088C AUGUST 2003 REVISED NOVEMBER 2003
www.ti.com
12
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages,
GVDD and PVDD_x.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turnon
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal LDRs to 3.3 V.
The gate-driver LDR can be bypassed for reducing idle
loss in the device by shorting GREG to GVDD and directly
feeding in 12.0 V. This can be useful in an application
where thermal conduction of heat from the device is
difficult. Bypassing the LDR reduces power dissipation.
PVDD_x is the H-bridge power supply pin. Two power pins
exist for each half-bridge to handle the current density. It
is very important that the circuitry
recommendations
around the PVDD_x pins are followed very carefully both
topology-
and
layout-wise.
For
topology
recommendations, see the System Configuration Used for
Characterization
section.
Following
these
recommendations is important for parameters like EMI,
reliability, and performance.
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
RESET
GVDD(1)
PVDD_x(1)
PWM_xP
> 1 ms
(1) PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are at this point
not charged. To comply with the click and pop scheme and
use of non-TI PWM processors it is recommended to use
a 4-k
pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor (see the System
Configuration Used for Characterization section).
After GVDD has been applied, it takes approximately 800
s to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
power stage bootstrap capacitor is charged.
RESET can now be released if the modulator is powered
up and streaming PWM signals to the power stage
PWM_xP.
A constant HIGH dc level on PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.
An unknown state of the PWM output signals from the
processor is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is de-asserted HIGH to
the power stage.
Powering Down
For power down of the power stage, an opposite approach
is necessary. RESET must be asserted LOW before the
valid PWM signal is removed.
When TI PWM processors are used in conjunction with TI
power stages, the correct timing control of RESET and
PWM_xP is performed by the modulator.
Precaution
The TAS5122 must always start up in the high-impedance
(Hi-Z) state. In this state, the bootstrap (BST) capacitor is
precharged by a resistor on each PWM output node to
ground.
See
System
Configuration
Used
for
Characterization. This ensures that the power stage is
ready for receiving PWM pulses, indicating either HIGH-
or LOW-side turnon after RESET is deasserted to the
power stage.
With the following pulldown and BST capacitor size the
charge time is:
C = 33 nF, R = 4.7 k
R
× C × 5 = 775.5 s
After GVDD has been applied, it takes approximately
800
s to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms the
power stage BST is charged and ready. RESET can now
be released if the PWM modulator is ready and is
streaming valid PWM signals to the power stage. Valid
PWM signals are switching PWM signals with a frequency
between 350400 kHz. A constant HIGH level on the
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TAS5122DFDG4 功能描述:音頻放大器 Digital Amplifier Power Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類(lèi)型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
TAS5122DFDR 功能描述:音頻放大器 Digital Amplifier Power Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類(lèi)型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
TAS5122DFDRG4 功能描述:音頻放大器 Digital Amplifier Power Stage RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類(lèi)型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
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TAS5132_07 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO DIGITAL AMPLIFIER POWER STAGE
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