
Architecture Overview
20
SLES090A—November 2003—Revised January 2004
TAS5076
Table 210. De-Emphasis Filter Characteristics
DEM_SEL2 (MSB)
DEM_SEL1
DESCRIPTION
0
De-emphasis disabled
0
1
De-emphasis enabled for Fs = 48 kHz
1
0
De-emphasis enabled for Fs = 44.1 kHz
1
De-emphasis enabled for Fs = 32 kHz
Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128
LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
0
10
Response
dB
3.18 (50
s)
10.6 (15
s)
f Frequency kHz
De-Emphasis
Figure 211. De-Emphasis Filter Characteristics
2.4
Pulse-Width Modulator (PWM)
The TAS5076 contains six channels of high performance digital Equibit PWM modulators that are designed
to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load)
configuration. The TAS5076 device uses noise shaping and sophisticated error correction algorithms to
achieve high power efficiency and high-performance digital audio reproduction.
The PWM provides six pseudodifferential outputs to drive six monolithic power stages (such as TAS5110) or
six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in single-ended
or bridged configurations. The TAS5076 also provides a high-performance differential output that can be used
to drive an external analog headphone amplifier.
2.4.1 Clipping Indicator
The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum
allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.
2.4.2 Error Recovery
Error recovery is used to provide error management and to permit the PWM output to be reset while preserving
all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by
bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit
in control register 1. Error recovery is a level-sensitive signal.
The device also performs an error recovery automatically:
When the speed configuration is changed to normal, double, or quad speed
Following a change in the serial data bus interface configuration
When ERR_RCVRY is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If
there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is
brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5076 begins normal operation. During error recovery, all
controls and device settings that were not updated are maintained in their current configurations.
To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between
the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay
can be selected to be either 6
s or 47 s.