- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98160 > TAS5066PAGG4 (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | TAS5066PAGG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 6/66頁 |
| 文件大?。?/td> | 1023K |
| 代理商： | TAS5066PAGG4 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Architecture Overview
8
SLES089—January 2004
TAS5066
If the master clock input can encounter a high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET must be applied during this time There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 21. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
DBSPD TERMINAL OR
CONTROL REGISTER BIT
MODE
SPEED SELECTION
0
Master or slave
Normal speed
0
1
Master or slave
Double speed
1
0
Master or slave
Quad speed
0
Slave
Quad speed if MCLK_IN = 128Fs
1
Master or slave
Error
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs:
Following a RESET when M_S terminal has a logic high applied
The transition to slave mode occurs:
Following a RESET when M_S terminal has a logic low applied
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5066 provides the master clock, SCLK, and LRCLK to the rest of
the system. In the master mode, the TAS5066 outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5066 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).
The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or
a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN
is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample
rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK
frequency is the data sample rate.
2.1.3.1
Crystal Type and Circuit
In clock master mode the TAS5066 can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5066 uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5066 as
shown in Figure 21.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS5076PFCG4 | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TAS5076PFCR | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TAS5076PFCRG4 | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TAS5076PFC | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| TAS5086DBT | SPECIALTY CONSUMER CIRCUIT, PDSO38 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5066PAGR | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5066PAGRG4 | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5076 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX-CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5076-5182C6EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5076-5182C6 EVAL MOD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TAS5076PFC | 功能描述:音頻 DSP 6-Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。