參數(shù)資料
型號(hào): TAS5066PAGG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 30/66頁(yè)
文件大小: 1023K
代理商: TAS5066PAGG4
Serial Control Interface Register Definitions
30
SLES089—January 2004
TAS5066
3.6
Automute Delay Register (0x05)
Table 37. Automute Delay Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Reserved
0
Set automute delay at 5 ms
0
1
Set automute delay at 10 ms
0
1
0
Set automute delay at 15 ms
0
1
Set automute delay at 20 ms
0
1
0
Set automute delay at 25 ms
0
1
0
1
Set automute delay at 30 ms
0
1
0
Set automute delay at 35 ms
0
1
Set automute delay at 40 ms
1
0
Set automute delay at 45 ms
1
1
Set automute delay at 50 ms
3.7
DC-Offset Control Registers (0x060x0B)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0A, and 0x0B).
Table 38. DC-Offset Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
0
Maximum correction for positive dc offset (–1.56% FS)
0
No dc-offset correction
0
1
Maximum correction for negative dc offset (1.56% FS)
3.8
Interchannel Delay Registers (0x0C0x11)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0C, 0x0D, 0x0E, 0x0F, 0x10, and 0x11).
The first channel delay is set at 0. Each subsequent channel has a default value that is 53 DCLKs larger than
the preceding channel.
Table 39. Six Interchannel Delay Registers
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
Minimum absolute delay, 0 DCLK cycles
Default for channel 1
0x00
0
1
0
1
0
1
Default for channel 2
0x35
0
1
0
1
0
1
0
Default for channel 3
0x6A
1
0
1
Default for channel 4
0x9F
1
0
1
0
Default for channel 5
0xD4
0
1
0
1
Default for channel 6
0x09
1
Maximum absolute delay, 255 DCLK cycles
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