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參數(shù)資料
| 型號： | TAS5036APFCRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Six Channel Digital Audio PWM Processor |
| 中文描述： | 六通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 14/62頁 |
| 文件大?。?/td> | 790K |
| 代理商： | TAS5036APFCRG4 |
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Architecture Overview
8
SLES061B—November 2002—Revised January 2004
TAS5036A
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET should be applied during this time. There are two recommended control
procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used.
These control sequences are shown in Section 4.
Table 21. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
DBSPD TERMINAL OR
CONTROL REGISTER BIT
MODE
SPEED SELECTION
0
0
Master or slave
Normal speed
0
1
Master or slave
Double speed
1
0
Master or slave
Quad speed
0
0
Slave
Quad speed if MCLK_IN = 128Fs
1
1
Master or slave
Error
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs following a RESET when M_S terminal has a logic high applied.
The transition to slave mode occurs following a RESET when M_S terminal has a logic low applied.
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5036A provides the master clock, SCLK, and LRCLK to the rest
of the system. In the master mode, the TAS5036A outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5036A device generates these clocks plus its internal clocks from the internal phase-locked loop
(PLL). The reference clock for the PLL can be provided by either an external clock source (attached to
XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached
to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the
data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master
mode. The LRCLK frequency is the data sample rate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS5036B_06 | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCG4 | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCR | Six Channel Digital Audio PWM Processor |
| TAS5036BPFCRG4 | Six Channel Digital Audio PWM Processor |
| TAS5100ADAP | Single Audio Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5036B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Precessor |
| TAS5036B_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Processor |
| TAS5036BPFC | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036BPFCG4 | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS5036BPFCR | 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
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