參數(shù)資料
型號: TAS5028PAG
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 58/86頁
文件大?。?/td> 1201K
代理商: TAS5028PAG
Serial Control Interface Register Definitions
53
SLES112 — June 2004
TAS5028
6
Serial Control Interface Register Definitions
Unless otherwise noted, the I2C register default values are in bold font.
Note that u indicates unused bits.
6.1
Clock Control Register (0x00)
Bit D1 is Don’t Care.
Table 6 - 1. Clock Control Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
-
32-kHz data rate
0
1
-
38-kHz data rate
0
1
0
-
44.1-kHz data rate
0
1
-
48-kHz data rate
1
0
-
88.2-kHz data rate
1
0
1
-
96-kHz data rate
1
0
-
176.4-kHz data rate
1
-
192-kHz data rate
-
0
MCLK frequency = 64
-
0
1
MCLK frequency = 128
-
0
1
0
MCLK frequency = 192
-
0
1
MCLK frequency = 256
-
1
0
MCLK frequency = 384
-
1
0
1
MCLK frequency = 512
-
1
0
MCLK frequency = 768
-
1
Reserved
-
1
Clock register is valid (read only)
-
0
Clock register is not valid (read only)
6.2
General Status Register 0 (0x01)
Table 6 - 2. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
-
Clip indicator
-
1
-
Bank switching busy
-
0
1
Identification code for TAS5028
6.3
Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and than read them to determine if there are any persistent errors.
Table 6 - 3. Error Status Register (0X02)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
-
PLL phase lock error
-
1
-
PLL auto lock error
-
1
-
SCLK error
-
1
-
LRCLK error
-
1
-
Frame slip
0
No errors
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