參數(shù)資料
型號: TAS5028PAG
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 47/86頁
文件大小: 1201K
代理商: TAS5028PAG
Serial Audio Interface Control and Timing
43
SLES112 — June 2004
TAS5028
3.7.2 Left Justified
Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64
× Fs is used to clock in the data. The first bit of data appears on the data lines at the same time
the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5028
masks unused trailing data bit positions.
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
9
8
5
4
1
0
MSB
LSB
23
22
32 Clks
LRCLK
Right Channel
9
8
5
4
1
0
MSB
LSB
NOTE: All data presented in 2s complement form with MSB first.
18
20-Bit Mode
5
4
1
0
19
14
16-Bit Mode
1
0
15
18
5
4
1
0
19
14
1
0
15
2-Channel Left-Justified Stereo Input
Figure 3 - 10. Left Justified 64 Fs Format
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