參數資料
型號: TAS5026APAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數: 21/64頁
文件大小: 936K
代理商: TAS5026APAGRG4
Architecture Overview
22
SLES068A—February 2003—Revised January 2004
TAS5026A
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset
present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of
±1.56% of full scale. The default value is zero correction represented by 00 (hex). These values can be
changed at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default
values are 0 for the first channel and 76 for each successive channel.
These values can be updated upon power up through the serial control interface. This delay is generated in
the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface.
NOTE:
The performance of a PurePath Digital
amplifier system is optimized by setting the PWM
timing based upon the type of back-end device that is used and the layout. These values are
set during initialization using the I2C serial interface.
2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5026A provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge tied load) configuration. The back-ends may be monolithic
power stages (such as the TAS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5026A
PWM_AP
PWM_AM
VALID
TAS5110
OUTA
OUTB
AP
AM
RESET
BP
BM
Speaker
Figure 212. PWM Outputs and H-Bridge Driven in BTL Configuration
2.5
I2C Serial Control Interface
MCLK must be active for the TAS5026A to support I2C bus transactions. The TAS5026A has a bidirectional
serial control interface that is compatible with the I2C (Inter IC) bus protocol and supports both 100 KBPS and
400 kbps data transfer rates for single and multiple byte write and read operations. This is a slave only device
that does not support a multi-master bus environment or wait state insertion. The control interface is used to
program the registers of the device and to read device status.
The TAS5026A supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus
operation (400 kHz maximum). The TAS5026A performs all I2C operations without I2C wait cycles.
PurePath Digital is a trademark of Texas Instruments.
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相關代理商/技術參數
參數描述
TAS5026CPAG 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR
TAS5026IPAG 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數量: 轉換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube
TAS5026IPAGG4 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數量: 轉換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube
TAS5026IPAGR 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數量: 轉換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube
TAS5026IPAGRG4 功能描述:多媒體雜項 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數量: 轉換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube