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參數(shù)資料
| 型號(hào)： | TAS5026APAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 14/64頁 |
| 文件大小： | 936K |
| 代理商： | TAS5026APAGRG4 |
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Architecture Overview
15
SLES068A—February 2003—Revised January 2004
TAS5026A
2.1.7.4
DSP Mode Timing
DSP mode timing uses an LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64
× Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5026A masks unused trailing data bit positions.
SCLK
LRCLK
64 SCLKS
LSB
MSB
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
SDIN
LSB
MSB
Figure 29. DSP Format
2.2
Reset, Power Down, and Status
The reset, power down, and status circuitry provides the necessary controls to bring the TAS5026A to the initial
inactive condition, achieve low power standby, and report system status.
2.2.1 Reset—RESET
The TAS5026A is placed in the reset mode by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5026A to its default conditions, sets the valid
16 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation
(there is no ramp down).
As long as the RESET terminal is held low, the device is in the reset state. During reset, all I2C and serial data
bus operations are ignored. Table 26 shows the device output signals while RESET is active.
Upon the release of RESET, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization
and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when
RESET is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active.
During device initialization all controls are reset to their initial states. Table 27 shows the control settings that
are changed during initialization.
RESET should be applied during power-up initialization or while changing the master slave clock states.
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PDF描述 |
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| TAS5026CPAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5026PAGR | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5026PAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5026PAGG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TAS5026IPAGRG4 | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5026CPAG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5026IPAG | 功能描述:多媒體雜項(xiàng) Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
| TAS5026IPAGG4 | 功能描述:多媒體雜項(xiàng) Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
| TAS5026IPAGR | 功能描述:多媒體雜項(xiàng) Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
| TAS5026IPAGRG4 | 功能描述:多媒體雜項(xiàng) Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube |
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