參數(shù)資料
型號: TAS5026APAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 32/64頁
文件大?。?/td> 936K
代理商: TAS5026APAGR
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
32
SLES068A—February 2003—Revised January 2004
TAS5026A
< 2 ms
MCLK
RESET
ERR_RCVRY
ERR_RCVRY and MUTE can
be set at any time prior to 2 ms
following the low-to-high
transition of RESET
MUTE
Wait a minimum of 100
s
after the low-to-high
transition of RESET
> 5 ms
Release ERR_RCVRY and
then MUTE when I2C
registers are programmed
Volume ramp
up 120 ms
Set serial interface format, data
rate, volume, ... via I2C
Figure 42. Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal
The operation of the TAS5026A can be tailored as desired to meet specific operating requirements by
adjusting the following:
Volume
Data sample rate
Emphasis/deemphasis settings
Individual channel mute
Automute delay register
DC-offset control registers
If desired, the TAS5026A can be set to perform an unmute sequence following the low-to-high transition of
the ERR_RCVRY terminal or the error recovery I2C command (register X03 bit D2). This capability is set by
writing x7F to the individual error recovery register (x04) and an x84 to x1F (a feature enable register).
4.2
Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less
than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register. If it is known at least 60 ms in advance that the sample rate changes, mute can be used to provide
a completely silent transition. The timing of this control sequence is shown in Figure 43 and Figure 44.
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