參數(shù)資料
型號(hào)： TAS5026APAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 24/64頁(yè)
文件大?。?/td> 936K
代理商： TAS5026APAGR
Architecture Overview
24
SLES068A—February 2003—Revised January 2004
TAS5026A
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
Start
Condition
Figure 214. Single-Byte Write Transfer
2.5.2 Multiple-Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5026A as shown in Figure 215. After receiving each data byte,
the TAS5026A responds with an acknowledge bit.
D7
D6
D1
D0 ACK
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Last Data Byte
A6
A5
A1
A0
R/W ACK A7
A5
A1
A0
ACK D7
D6
D1
D0 ACK
Start
Condition
Acknowledge
First Data Byte
A4
A3
A6
Other
Data Bytes
Figure 215. Multiple-Byte Write Transfer
2.5.3 Single-Byte Read
As shown in Figure 216, a single byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed
by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is 0. After receiving the TAS5026A address and the read/write
bit, the TAS5026A responds with an acknowledge bit. Also, after sending the internal memory address byte
or bytes, the master device transmits another start condition followed by the TAS5026A address and the
read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5026A
and the read/write bit, the TAS5026A again responds with an acknowledge bit. Next, the TAS5026A transmits
the data byte from the memory address being read. After receiving the data byte, the master device transmits
a not acknowledge followed by a stop condition to complete the single byte data read transfer.
A6
A5
A0
R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Data Byte
D7
D6
D1
D0 ACK
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Not
Acknowledge
R/W
A1
Figure 216. Single-Byte Read
2.5.4 Multiple-Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes
are transmitted by the TAS5026A to the master device as shown in Figure 217. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte.
A6
A0
ACK
Acknowledge
I2C Device Address and
Read/Write Bit
R/W
A6
A0
R/W ACK
A4
A0
ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
Last Data Byte
D7
D6
D1
D0
ACK
First Data Byte
Repeat Start Condition
Not
Acknowledge
I2C Device Address and
Read/Write Bit
Register Address
Other
Data Bytes
A7
A6
A5
Figure 217. Multiple-Byte Read
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