參數(shù)資料
型號(hào): TAS5026APAG
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 33/64頁
文件大小: 936K
代理商: TAS5026APAG
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
33
SLES068A—February 2003—Revised January 2004
TAS5026A
MCLK
MUTE
Terminal
DBSPD
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock Transition
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp
Up 42 65 ms
> 5 ms
< 2 ms
Volume Ramp
Down 42 65 ms
Set within 2 ms
of transition
Figure 43. Changing the Data Sample Rate Using the DBSPD Terminal
MCLK
MUTE
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Clock Transition
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp
Up 42 65 ms
> 5 ms
< 2 ms
Volume Ramp
Down 42 65 ms
ERR_RCVRY
Terminal
Hold ERR_RCVRY low
to give additional timeset registers
Set data rate via I2C
register 0x02, D7 and D6
Figure 44. Changing the Data Sample Rate Using the I2C
However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then
RESET should be applied during this time. There are two recommended control procedures for this case,
depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences
are shown in Figure 45 and Figure 46.
Because this sequence employs the RESET terminal, the internal register settings are set to the default
values.
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