參數(shù)資料
型號(hào): TAS5026
廠商: Texas Instruments, Inc.
英文描述: Digital Audio PWM Processor
中文描述: 數(shù)字音頻 PWM 處理器
文件頁數(shù): 33/48頁
文件大?。?/td> 689K
代理商: TAS5026
System Initialization
28
SLES041B
November 2002
TAS5026
4
System Initialization
Reset is used during system initialization to hold the TAS5026 inactive while power (VDD), the master clock
(MCLK_IN), the device control, and the data signals become stable. The recommended initialization
sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control
signals (MUTE, PDN, M_S, ERR_RCVRY,,DBSPD, and CS0) are stable.
MCLK
VDD
3 V
24 MCLK_IN
Cycles
RESET
Figure 4
1. RESET During System Initialization
The serial data interface format is then set through the serial data interface control register using the serial
control interface.
At this point the TAS5026 is fully operational. However, the operation of the TAS5026 can be tailored as
desired to meet specific operating requirements by adjusting the following:
Automute delay register
DC-Offset control registers
Interchannel delay registers
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