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參數(shù)資料
| 型號： | TAS5026 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Audio PWM Processor |
| 中文描述： | 數(shù)字音頻 PWM 處理器 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TAS5026 |
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Architecture Overview
10
SLES041B
—
November 2002
TAS5026
2.1.5 PLL Filter
A low jitter PLL produces the internal timing of the TAS5026 (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external loop filter are provided through PLL_FLT_OUT and
PLL_FLT_RET as shown in Figure 2
–
2.
PLL_FLT_OUT
TAS5026
PLL_FLT_RET
220
47 nF
4.7 nF
Figure 2
–
2. External PLL Loop Filter
2.1.6 DCLK
DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5026 uses
the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times
MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
2
C addressable registers, DCLK
clock cycles are used to specify Interchannel delay and to detect when the MCLK is frequency is drifting.
Table 2
–
4 DCLK shows the relationship between Sample Rate, MCLK and DCLK.
Table 2
–
4. DCLK
FS
(kHz)
32
MCLK
(MHz)
8.1920
DCLK
(MHz)
65.5360
DCK Period
(ns)
15.3
44.1
11.2896
90.3168
11.1
48
12.2880
98.3040
10.2
88
22.5280
90.1120
11.1
96
24.5760
98.3040
10.2
192
49.1520
98.3040
10.2
2.1.7 Serial Data Interface
The TAS5026 operates as a slave only/receive only serial data interface in all modes. The TAS5026 has three
PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The
serial audio data is in MSB first; 2
’
s complement format.
The serial data interfaces of the TAS5026 can be configured in right justified, I
2
S, left-justified, or DSP modes.
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register. The supported word
lengths are shown in Table 2
–
5.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS5026CPAG | SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5026IPAG | SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5036CPAG | SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5101IDAP | Single Audio Amplifier |
| TAS5101IDAPR | Single Audio Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5026A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six-Channel Digital Audio PWM Processor |
| TAS5026APAG | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5026APAGG4 | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5026APAGR | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5026APAGRG4 | 功能描述:音頻 DSP 6Ch Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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