參數資料
型號: TAS5015IPFB
廠商: Texas Instruments, Inc.
元件分類: 運動控制電子
英文描述: TRUE DIGITAL AUDIO AMPLIFIER TAS5015 DIGITAL AUDIO PWM PROCESSOR
中文描述: 真正的數字音頻放大器TAS5015數字音頻PWM處理器
文件頁數: 10/19頁
文件大?。?/td> 240K
代理商: TAS5015IPFB
TAS5015
SLES017
SEPTEMBER 2001
10
www.ti.com
functional description (continued)
Table 4. Hardware Selection of Serial Audio Modes
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
SERIAL INTERFACE
SDIN
16-bit, MSB first; right justified
20-bit, MSB first; right justified
24-bit, MSB first; right justified
16-bit IIS
20-bit IIS
24-bit IIS
16-bit MSB first, left justified
16-bit DSP frame
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The following figures illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded
with binary 0s.
MSB first, right-justified (for 16, 20, 24 bits)
X
MSB
LSB
MSB
LSB
SCLK
LRCLK = fs
SDIN
Left Channel
Right Channel
X
Figure 7. MSB First Right Justified
Note the following characteristics of this protocol.
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
SDIN is sampled at the rising edge of SCLK.
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參數描述
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