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參數(shù)資料
| 型號： | TAS3103EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Evaluation Module for Digital Audio Processor With 3D Effects(帶3維效果的數(shù)字音頻處理器TAS3103的評估模塊) |
| 中文描述： | 評估模塊用于數(shù)字音頻處理器，3D音效（帶3維效果的數(shù)字音頻處理器TAS3103的評估模塊） |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 90K |
| 代理商： | TAS3103EVM |
SCLK Routing Switches
2-6
If TAS3103
–
U1 is the source of MCLK and this clock is being supplied to the
I
2
S input port, S8 must be set to L. The architecture of the TAS3103 allows it
to be the source of MCLK and yet be slaved to external SCLK and LRCLK
clocks. This means that TAS3103
–
U1 can supply MCLK to an external device
connected to the I
2
S input port and operate as a slave using SCLK and LRCLK.
MCLKO of TAS3103
–
U1 is also used to source MCLKI for TAS3103
–
U2.
MCLKO of TAS3103
–
U2 supplies MCLK to the I
2
S output header and to a
divide-by-2 flip-flop whose output provides MCLK to the SPDIF Tx (all devices
except the SPDIF Tx use a 256 Fs MCLK; the SPDIF Tx uses a 128 Fs MCLK).
For TAS3103
–
U2, MCLKO must remain in its power-on default state of
MCLKO = MCLKI.
On the EVM, the TAS3103
’
s MCLKO output serves as a buffer for the
distribution of MCLK. These additional sources of MCLK allow optimal MCLK
distribution topologies to be achieved and clock trace noise management
goals to be realized.
The I
2
S input port can serve as either a master port, a slave port, or a mixed
port whereby MCLK is provided to an external device, but SCLK and LRCLK
are provided by the external device. The I
2
S output port, on the other hand,
is strictly a slave port that outputs MCLK, SCLK, and LRCLK, along with data,
to external devices.
Caution
TAS3103
–
U1 can serve as either a master or slave device. TAS3103
–
U2 must always be a slave device.
2.3
SCLK Routing Switches
Figure 2
–
4 illustrates the SCLK options provided by the EVM. As is the case
for MCLK, there are three choices for sourcing SCLK
—
SPDIF Rx, I
2
S input
header, and TAS3103
–
U1. Again, if the SPDIF Rx is used to source SCLK, it
must also source MCLK and LRCLK.
S3 selects between the SPDIF Rx SCLK (S3 = H) and an I
2
S input port SCLK
(S3 = L). The output of the S3 selection is directly routed to pin SCLKIN of
TAS3103
–
U1. If the I
2
S input port is used to source SCLK, S9 must be set to
H to place in a 3-state condition the driver used to supply SCLK to an input
device connected to the I
2
S input port.
There are two SCLK output pins on each TAS3103. SLCKOUT1 is used to
clock serial data into the TAS3103 and SCLKOUT2 is used to clock data out
of the TAS3103. Two separate clocks are necessary since the input and output
data bit rates can be different. An application using a discrete in/TDM out
topology results in a higher frequency output clock than the input clock
(SCLKOUT2 > SCLKOUT1). An application using a TDM in/discrete out
topology results in a higher frequency input clock than the output clock
(SCLKOUT2 < SCLKOUT1). If the TAS3103 is in the slave mode (the
power-on default state), SCLKOUT1 and SCLKOUT2 are derived from
SCLKIN. If SCLKOUT 1
≠
SCLKOUT2, SCLKIN must be equal to the higher
of the two clocks. If the TAS3103 is in the master mode, both SCLKOUT1 and
SCLKOUT2 are derived from (MCLKI OR XTALI).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TAS3103IDBT | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTR | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3103IDBTRG4 | 功能描述:音頻 DSP Digital Audio Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TAS3108 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO DIGITAL SIGNAL PROCESSORS |
| TAS3108DCP | 功能描述:音頻 DSP 8-Channel Audio DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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