
T E C H N I C A L I N F O R M A T I O N
24
TA3020, Rev 2.1, 01.01
One apparent method to generate the VN10 supply voltage is to use a negative IC regulator to drop
PGND down to 10V (relative to VNN). This method will not work since negative regulators only sink
current into the regulator output and will not be capable of sourcing the current required by VN10.
Furthermore, problems can arise since VN10 will not track movements in VNN.
Output Transistor Selection
The key parameters to consider when selecting what MOSFET to use with the TA3020 are drain-
source breakdown voltage (BVdss), gate charge (Qg), and on-resistance (R
DS(ON)
).
The BVdss rating of the MOSFET needs to be selected to accommodate the voltage swing between
V
SPOS
and V
SNEG
as well as any voltage peaks caused by voltage ringing due to switching transients.
With a ‘good’ circuit board layout, a BVdss that is 50% higher than the VPP and VNN voltage swing
is a reasonable starting point. The BVdss rating should be verified by measuring the actual voltages
experienced by the MOSFET in the final circuit.
Ideally a low Qg (total gate charge) and low R
DS(ON)
are desired for the best amplifier performance.
Unfortunately, these are conflicting requirements since R
DS(ON)
is inversely proportional to Qg for a
typical MOSFET. The design trade-off is one of cost versus performance. A lower R
DS(ON)
means
lower I
2
R
DS(ON)
losses but the associated higher Qg translates into higher switching losses (losses =
Qg x 10 x 1.2MHz). A lower R
DS(ON)
also means a larger silicon die and higher cost. A higher R
DS(ON)
means lower cost and lower switching losses but higher I
2
R
DSON
losses.
The following table lists BVdss, Qg and R
DS(ON)
for MOSFETs that Tripath has used with the
TA3020:
Manufacturer
Manufacturer’s
Part Number
ST Microelectronics
STW34NB20
200
ST Microelectronics
STP19NB20
200
International Rectifier
IRFB41N15D
150
International Rectifier
IRFB31N20D
200
Fairchild
FQA34N20
200
Gate Resistor Selection
The gate resistors, R
G
, are used to control MOSFET switching rise/fall times and thereby minimize
voltage overshoots. They also dissipate a portion of the power resulting from moving the gate
charge each time the MOSFET is switched. If R
G
is too small, excessive heat can be generated in
the driver. Large gate resistors lead to slower MOSFET switching, which requires a larger break-
before-make (BBM) delay.
Break-Before-Make (BBM) Timing Control
The half-bridge power MOSFETs require a deadtime between when one transistor is turned off and
the other is turned on (break-before-make) in order to minimize shoot through currents. BBM0 and
BBM1 are logic inputs (connected to logic high or pulled down to logic low) that control the break-
before-make timing of the output transistors according to the following table.
BVdss
Qg
(nanoCoulombs)
60
29
67
70
60
R
DS(ON)
(Max)
(Ohms)
0.075
0.18
0.045
0.082
0.075