參數(shù)資料
型號: T89C51CC02UA-SITIM
廠商: Atmel
文件頁數(shù): 4/159頁
文件大小: 0K
描述: IC 8051 MCU FLASH 16K 28PLCC
標(biāo)準(zhǔn)包裝: 37
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-PLCC
包裝: 管件
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC02UASITIM
101
AT/T89C51CC02
4126L–CAN–01/08
Table 66. CANBT2 Register
CANBT2 (S:B5h) – CAN bit Timing Registers 2
Note:
1. The CAN controller bit timing registers must be accessed only if the CAN controller is
disabled with the ENA bit of the CANGCON register set to 0.
No default value after reset.
765
43210
-
SJW 1
SJW 0
-
PRS 2
PRS 1
PRS 0
-
Bit Number
Bit Mnemonic
Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 - 5
SJW1:0
Re-synchronization Jump Width
To compensate for phase shifts between clock oscillators of
different bus controllers, the controller must re-synchronize on any
relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of
clock cycles. A bit period may be shortened or lengthened by a re-
synchronization.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - 1
PRS2:0
Programming Time Segment
This part of the bit time is used to compensate for the physical
delay times within the network. It is twice the sum of the signal
propagation time on the bus line, the input comparator delay and
the output driver delay.
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Tsjw = Tscl x (SJW [1..0] +1)
Tprs = Tscl x (PRS[2..0] + 1)
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