參數(shù)資料
型號(hào): T89C51AC2-SLSIM
廠商: Atmel
文件頁數(shù): 109/121頁
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
88
A/T89C51AC2
4127H–8051–02/08
ADC Converter
Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (see Figure 48). Clear this flag for re-
arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.(1)
Note:
1. Always leave Tsetup time before starting a conversion unless ADEN is permanently
high. In this case one should wait Tsetup only before the first conversion.
Table 62. Selected Analog input
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note:
ADCIN should not exceed VAREF absolute maximum range (see “Absolute Maximum
Clock Selection
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
if PRS > 0 then fADC = Fperiph / 2 x PRS
if PRS = 0 then fADC = Fperiph / 64
SCH2
SCH1
SCH0
Selected Analog input
0
AN0
0
1
AN1
0
1
0
AN2
0
1
AN3
1
0
AN4
1
0
1
AN5
1
0
AN6
1
AN7
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