參數(shù)資料
型號(hào)： T8536B
元件分類： Codec
英文描述： T8535B/T8536B Quad Programmable Codec
中文描述： T8535B/T8536B四可編程編解碼器
文件頁數(shù)： 43/50頁
文件大?。?/td> 929K
代理商： T8536B
Agere Systems Inc.
43
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Software Interface
(continued)
Table 21. Control Bit Definition
(continued)
Control Name
(Address, Decimal)
[Address, Hex]
GTX1
(153—154)
[0x99—0x9a]
TXBITOFF
(155)
[0x9b]
Bit
Assignment(s)
Function
0—11
Gain control for tweak gain stage in transmit direction. Defaults to
0x051a (2.11 dB). This is a 12-bit multiply operation with a maximum
gain of four (12 dB).
Transmit direction bit offset for the FS signal. Defaults to zero. These
3 bits can be thought of as the least significant bits (TXOFF contains the
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.
Load as zeros.
Transmit time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits; allow for two time slots when using linear
mode or double-clock mode.
3-state transmit PCM interface. Defaults to zero. A one forces the PCM
interface into a high-impedance state during its assigned time-slot on
the PCM bus. Placing the channel in standby mode also forces a high-
impedance condition on the transmit interface.
Transmit zeros instead of data. Defaults to zero (off).
Linear mode significant bit. A one sets MSB first for both PCM transmit
data output and for PCM receive data input. A zero sets both PCM
paths to LSB first. Defaults to zero, LSB first.
Place idle-channel code on receive path. Defaults to zero (off).
Loopback receive to transmit at PCM conversion interface (
digital
loopback 1
). Defaults to zero (no loopback).
Loopback transmit to receive at PCM conversion interface (
analog
loopback 2
). Defaults to zero (no loopback).
Linear/companded mode. A one sets 16-bit linear mode with two adja-
cent time slots used. Linear data is in two’s complement form. Linear
mode is only available when using single-clocking mode. A zero sets
companded mode with only one time slot used. Defaults to zero. Linear
mode is programmed as LSB or MSB first using bit 5 of this word.
μ
-law or A-law. A one sets A-law mode, and a zero sets
μ
-law mode.
Defaults to zero (
μ
-law).
Load as zeros.
Controls the drivers for the corresponding SLIC latches. A one enables
the lead as an output. Defaults to 0x0C (bits 2 and 3 set, the rest
cleared).
Load as zeros.
SLIC data latches. If the corresponding bit in the SLICTS address is set
for an output, the device will drive the corresponding bit according to the
contents of this address. Writes are performed within 125
μ
s. Wait
125
μ
s before a subsequent write to the same channel or between
write
all channel
commands. Default is zero.
Not used, ignore on read.
Reports the actual state of the SLIC leads. Anything written to this
address is ignored. Updates within 125
μ
s.
Test location for serial interface. This location has no internal use, but
merely latches write data for the purpose of testing the serial interface.
This register does not clear with reset.
5—7
0—4
0—7
TXOFF
(156)
[0x9c]
PCMCTRL1
(157)
[0x9d]
7
6
5
4
3
2
1
0
SLICTS
(158)
[0x9e]
6—7
0—5
SLICWR
(159)
[0x9f]
6—7
0—5
SLICRD
(160)
[0xa0]
6—7
0—5
VERIFY
(162)
[0xa2]
0—7
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