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參數(shù)資料
| 型號： | T8536B |
| 元件分類： | Codec |
| 英文描述： | T8535B/T8536B Quad Programmable Codec |
| 中文描述： | T8535B/T8536B四可編程編解碼器 |
| 文件頁數(shù)： | 40/50頁 |
| 文件大?。?/td> | 929K |
| 代理商： | T8536B |
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40
Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Software Interface
Table 20. Memory Mapping
With the exceptions noted, all of these memory locations may be read to determine the state of the controls con-
tained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most
significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the mem-
ory locations can be programmed on a per-channel basis.
Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.
Control
Name
Address
(Decimal)
# of
Bits
Used
448
Default
Value
Description
HBALTAPS
0—27
64—91
28—63
92—127
128
See Table 21
Balance impedance tap coefficients.
Reserved
—
—
These addresses have no function.
RESCTRL
2
0x00
Reset address. Writing a one in the used positions causes a
reset as defined by the bit definition. This reset remains in
force until the bit is written as a zero.
Standby/active control.
Bit offset for receive direction.
16 * channel # Time-slot assignment for receive direction.
0x0400
Gain transfer for receive direction.
0x01ac
Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, receive direction.
—
This address has no function.
07ed0000
CTZ bleed coefficients.
—
This address has no function.
0x00
PCM transmission and sampling edge control.
0x19
RTZ, transmit analog gain (XAG), and digital loopback 3
controls.
17 * channel # Internal time-slot interchanger and loopback controls.
Default sets external pins to state referenced in this data
sheet.
0x0400
Gain transfer for transmit direction.
0x000000
Transmit line equalization.
0x051a
Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, transmit direction.
0x00
Bit offset for transmit direction.
16 * channel # Time-slot assignment for transmit direction.
0x00
PCM, companding, and loopback controls.
0x0c
SLIC 3-state control. Latch I/O.
0x00
Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.
—
Current actual state of the SLIC leads. This will be the same
as SLICWR for those leads configured as outputs. All other
positions will reflect the actual state of the external lead. A
write operation to this word will be ignored, and within one
PCM frame (125
μ
s), the data will be overwritten.
—
This address has no function.
0x00
Test address for serial interface verification.
CHACTIVE
RXBITOFF
RXOFF
GRX1
GRX2
129
130
131
1
4
8
11
11
0x00
0x00
132—133
134—135
Reserved
CTZCTRL
Reserved
PCMCTRL2
SDCTRL
136—139
140—143
144
145
146
—
31
—
6
7
SDTSI
147
7
GTX2
ZEQTX
GTX1
148—149
150—152
153—154
12
21
12
TXBITOFF
TXOFF
PCMCTRL1
SLICTS
SLICWR
155
156
157
158
159
4 or 5
8
7
6
6
SLICRD
160
6
Reserved
VERIFY
161
162
—
8
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