參數(shù)資料
型號(hào): T8531
元件分類: Codec
英文描述: T8502 and T8503 Dual PCM Codecs with Filters
中文描述: T8502和T8503雙的PCM編解碼器與濾波器
文件頁(yè)數(shù): 29/48頁(yè)
文件大小: 999K
代理商: T8531
Lucent Technologies Inc.
29
Preliminary Data Sheet
November 2000
Codec Chip Set
T8531/T8532 Multichannel Programmable
Timing Characteristics
A signal is valid if it is above V
IH
or below V
IL
and invalid if it is between V
IL
and V
IH
. For the purposes of this spec-
ification, the following conditions apply:
I
All input signals are defined as V
IL
= 0.4 V, V
IH
= 2.7 V, tR < 10 ns, tF < 10 ns.
I
tR is measured from V
IL
to V
IH
. tF is measured from V
IH
to V
IL
.
I
Delay times are measured from the input signal valid to the output signal valid.
I
Setup times are measured from the data input valid to the clock input invalid.
I
Hold times are measured from the clock signal valid to the data input invalid.
I
Pulse widths are measured from V
IL
to V
IL
or from V
IH
to V
IH
.
Table 16. PCM Interface Timing
(See Figure 9.)
Symbol
fSCK
Parameter
Test Conditions
Min
Typ
2.048
4.096
Max
Unit
MHz
MHz
Frequency of SCK (Selection
frequency is pin-strap
programmable.)
Period of SCK
Jitter of SCK
tSCK
Measured from V
IL
to V
IL
1/fSCK
ns
100 ns in
100 ms = 1 ppm
15
15
tSCHSCL
tSCLSCH
tSCH1SCH2 Rise Time of SCK
tSCL2SCL1
Fall Time of SCK
tFSHFSL
Period of SFS High
Period of SCK High
Period of SCK Low
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
Measured from V
IH
to V
IL
:
2.048 MHz
4.096 MHz
0 < C
LOAD
< 100 pF
80
80
ns
ns
ns
ns
0.488
0.244
30
30
0
30
30
9
62.5
62.5
90
μ
s
μ
s
ns
ns
ns
ns
ns
tSFHSCL
tSCLSFL
tSCHDXV
tDRVSCL
tSCLDRX
Frame Sync High Setup
Frame Sync Hold Time
Data Enabled on TS Entry
Receive Data Setup
Receive Data Hold
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