參數(shù)資料
型號(hào)： T71L6808A
廠(chǎng)商： TM Technology, Inc.
英文描述： Octal 10/100 Switch with Embedded Memory
中文描述： 八路10/100交換機(jī)嵌入式存儲(chǔ)器
文件頁(yè)數(shù)： 14/23頁(yè)
文件大?。?/td> 335K
代理商： T71L6808A
TE
CH
tm
Management Interface (MI)
MDC
Preliminary T71L6808A
Taiwan Memory Technology, Inc. reserves the right
P. 14
to change products or specifications without notice.
Publication Date:May. 2001
Revision:0.A
O
43
Management Interface (MI) Clock Output.
This MI clock shifts serial data in and out of MDIO on rising
edges from an external Physical Layer device.
Management Interface (MI) Data I/O.
This bi-directional pin contains serial data that is clocked in and
out on rising edges of the MDC clock from an external Physical
Layer device.
MDIO
I/O
44
Serial EEPROM 24LC02 Interface
SCLK
O
121
Serial Clock.
Internally pulled high.
Serial Data Input/Output.
Internally pulled high.
SDA
I/O
122
Mode Pins (Reset-read)
ENBKPRS
I
107
Enable Half Duplex Back Pressure Function.
Pulled high upon reset will enable the back pressure function.
Pulled low upon reset will disable the back pressure function.
Enable Full Duplex Flow Control.
Pulled high upon reset will enable the full duplex IEEE802.3x
flow control function. The flow control ability will be write to
the management register 4 of PHY device one and only one
time after power-on reset, for advertising.
Pulled low upon reset will disable the flow control function.
ENFCTRL
I
112
Test Pin
TEST
I
106
Test Pin.
For internal use. Must be tied to ground for normal use.
33, 41, 42
Test Pin.
For internal use.
56
SSRAM Test Output.
For internal test.
57
SSRAM Test Output.
For internal test.
55
Test Pin.
For internal use. Must be tied to ground for normal use.
125
Test Pin.
For internal use. Must be tied to ground for normal use.
TEST_MOD
[2:0]
TEST_OP1
I
O
TEST_OP2
O
ARL_LOOP
I
ARL_PAIR
I
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