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參數(shù)資料
| 型號： | T71L6808A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | Octal 10/100 Switch with Embedded Memory |
| 中文描述： | 八路10/100交換機(jī)嵌入式存儲(chǔ)器 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 335K |
| 代理商： | T71L6808A |
TE
CH
tm
Preliminary T71L6808A
Taiwan Memory Technology, Inc. reserves the right
P. 10
to change products or specifications without notice.
Publication Date:May. 2001
Revision:0.A
24LC02 Device Operation
Clock and Data transitions: The SDA pin is normally pulled high with an external register. Data on
the SDA pin may change only during SCL low time periods. Data changes during SCL high periods
will indicate a start or stop condition as defined below.
Start condition
: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command.
Stop condition
: A low-to-high transition of SDA with SCL high is a stop condition.
Acknowledge
: All addresses and data words are serially transmitted to and from the EEPROM in 8
bit words. The 24LC02 sends a zero to acknowledge that it has received each word. This happens
during the ninth clock cycle.
Random Read
: A random read requires a "dummy" byte write sequence to load in the data word
address.
Sequential Read
: For T71L6808A, the sequential reads are initiated by a random address read.
After the 24LC02 receives a data word, it responds with an acknowledge. As long as the 24LC02
receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words.
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