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參數(shù)資料
| 型號： | T7115A |
| 廠商： | Lineage Power |
| 英文描述： | Synchronous Protocol Data Formatter(同步協(xié)議數(shù)據(jù)格式化芯片) |
| 中文描述： | 同步協(xié)議數(shù)據(jù)格式化（同步協(xié)議數(shù)據(jù)格式化芯片） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 185K |
| 代理商： | T7115A |
Product Brief
March 1997
T7115A Synchronous Protocol Data Formatter
Features
Serial Port Interface
I
32-channel (full-duplex), multiplexed, serial
input/output HDLC processing
I
Support for T1/DS1 24-channel and CEPT/E1
32-channel modes
I
Automatic flag transmission and detection
I
Flag stuffing up to 2,047 flags
I
Flag adjustment for synchronous rate adaption
I
Full, partial, or no CRC generation and checking
I
Zero-bit insertion and deletion
I
Abort/idle detection and transmission
I
Long-frame detection
I
2 Mbits/s continuous serial data rate
I
Transparent mode (no protocol) supports ECMA
102 and ITU-T I.463 RA2 rate adaption standards
I
Dynamic channel allocation (or channel
concatenation) supports DS0, H0, H11, and H12
channels and other channel rates
I
Bit-rate control on each channel
I
Channel inversion
I
Loopback mode
I
DMA CRC for relay mode
Microprocessor Interface
I
Compatibility with 16-bit or 32-bit microprocessor
systems
I
On-chip, 64-channel, DMA memory address gen-
erator and buffer manager
I
Interrupt queue (up to 4,096 interrupts)
I
Nonmultiplexed 16-bit data and 24-bit address
(8 Mwords) buses
I
Transmit and receive buffers accessible through
memory-mapped look-up tables
Description
5-4457(C).a
Figure 1. Simplified Block Diagram
T7115A–MC
T7115A–ML
(SPYDER-T)
TD
TCLK
TISYN
RD
RCLK
RISYN
ADDRESS BUS
A[23:0]
DATA BUS
D[15:0]
RST
INT
SA
CLK
TEST
DREQ
DACK
AVAL
RE
WE
24
16
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