
T6B65AFG
2005-06-01
5
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Z-address counter
The Z-address counter holds the 6-bit datum that indicates the display start line. This value is preset by the
PM signal. The value indicates the address of the display start line, which is the line that appears at the top
of the screen.
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Counter Up / Down register
This register determines the counter and Up / Down mode. When the X-counter / Up mode is selected,
reading or writing to the RAM causes the X-counter to increment automatically.
When the X-counter / Down mode is selected, reading or writing to the RAM causes the X-counter to
decrement automatically. When the Y-counter / Up mode is selected, reading or writing to the RAM causes
the Y-counter to increment automatically. When the Y-counter / Down mode is selected, reading or writing to
the RAM causes the Y-counter to decrement automatically.
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Display ON / OFF register
This 1-bit register holds the ON / OFF state. In the OFF state, the output is ignored. In the ON state, the
data in the display RAM is displayed.
The data in the display RAM is independent of the value of the display ON / OFF setting.
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Busy flag
The Busy flag is set when an instruction other than the Status Read instruction is executed. Using Status
Read, you can find out whether the Busy flag has been set or not. While the Busy flag is set, the T6B65A
cannot accept any instruction other than Status Read.
Ensure, therefore, that the Busy flag is reset before an instruction is issued.
The Busy state time (T) is always as follows:
1 / F
≤
T
≤
2 / F [seconds] F:
φ
frequency (one half of the T6B66BFG's oscillation frequency)
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Latch
The rising edge of CL latches data from the display RAM.
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Column driver circuit and LCD voltage generation circuit
The column driver circuit consists of 80 driver circuits. The combination of display data from latches and the
M signal selects one of the four LCD levels. Details of the voltage generation circuit and column driver
circuit are shown in the diagram below: