
TE
CH
tm
OPERATION 
VD1/Over-Charge Detector
    The VD1 monitors VDD pin voltage. When the 
VDD voltage crosses over charge detector threshold 
VDET1 from a low value to a value higher than the 
VDET1, the VD1 can sense a over-charging and an 
external charge control Nch-MOS-FET turns to 
“OFF” with Cout pin being at “L” level. 
    There can be two cases to reset the VD1 making 
the Cout pin level to “H” again after detecting 
over-charge. Resetting the VD1 can make charging 
system allowable to resumption of charging process. 
The first case is in such conditions that a time when 
the VDD voltage is coming down to a level lower 
than “VREL1”. While in the second case, 
connecting a kind of loading to VDD after 
disconnecting a charger from the battery pack can 
make the VD1 resetting when the VDD level is in 
between “VDET1” and “VREL1”. 
     After detecting over-charge with the VDD 
voltage of higher than VDET1, connecting system 
load to the battery pack makes load current 
allowable through parasitic diode of external charge 
control FET. The Cout level would be high when the 
VDD level is coming down to a level below the 
VDET1 by continuous drawing of load current. 
    When the VDD level is going up to a higher level 
than VDET1 if the VDD voltage would be back to a 
level lower than the VDET1 within a time period of 
the output delay time, VD1 would not output a signal 
for turning off the charge control FET. 
A level shifter incorporated in a buffer driver for the 
Cout pin makes the “L” level of Cout pin to the V- 
pin voltage and the “H” level of Cout pin is set to 
VDD voltage with CMOS buffer 
                                                                      T63H0006B
TM Technology Inc. reserves the right
P. 4                                    
Publication Date: JUN. 2004 
to change products or specifications without notice.                                                                         Revision:B
VD2/Over-Discharge Detector
    The VD2 is monitoring a VDD pin voltage. When 
the VDD voltage crosses the over-discharge detector 
threshold VDET2 from a high value to a value lower 
than the VDET2, the VD2 can sense an 
over-discharging and the external discharge control 
Nch MOSFT turns to “OFF” with the Dout pin being 
at “L” level. 
    To reset the VD2 with the Dout pin level being 
“H” again after detecting over-discharge it is 
necessary to connect a charger to the battery pack for 
T63H0006B. When the VDD voltage stays under 
over-discharge detector threshold VDET2 charge 
current can flow through parasitic diode of external 
discharge control MOSFET, then after the VDD 
voltage comes up to a value larger than VDET2, 
Dout becomes “H” and discharging process would 
be able to advance through ON state MOSFET for 
discharge control. 
    Connecting a charger to the battery pack makes 
the Dout level being “H” instantaneously when the 
VDD voltage is higher than VDET2. 
    Besides, for T63H0006B, when a cell voltage 
reaches equal or more than over-discharge released 
voltage, or VDET2, over-discharge condition can be 
also released. 
    An output delay time for the over-discharge 
detection is fixed internally, tVDET2 =10ms typ. At 
VDD=2.4V. When the VDD level is going down to a 
lower level than VDET2 if the VDD voltage would 
be back to a level higher than the VDET2 within a 
time period of the output delay time, VD2 would not 
output a signal for turning off the discharge control 
FET. 
    After detection of an over-discharge by VD2, 
supply current would be reduced to typ. 0.15uA at 
VDD=2.0V and into standby, only the charger 
detector is operating. 
    The output type of Dout pin is CMOS having “H” 
level of VDD and “L” level of Vss.