
TE
CH
tm
which enables charge control Nch-MOS-FET 
for turning to “OFF”. Though the VDD voltage 
would be going up to a higher level than Vdet1 if 
it is within a time period of the output delay time, 
VD1 would not be output a signal for turning 
Reset conditions from overcharging 
There can be two cases to reset the VD1 making 
the Cout pin level to “H” again after detecting 
overcharge. Resetting the VD1 makes the 
charging system ready for resumption of 
charging process. 
The first case is in such condition that a time 
when the VDD voltage is coming down to a 
level lower than “Vdet1-Vhys1”. While in the 
second case, disconnecting a charger from the 
battery pack can make the VD1 resetting when 
VD2/Over-Discharge Detector 
The VD2 monitors a VDD pin voltage. When 
the VDD voltage crosses the over-discharge 
detector threshold Vdet2 from a high value to a 
value lower than the Vdet2, the VD2 can sense 
an over-discharging and the external discharge 
control Nch-MOS-FET turns to “OFF” with 
Dout pin being at “L”. 
Resetting the VD2 with the Dout pin level being 
“H” again after detecting over-discharge is only 
possible by connecting a charger to the battery 
VDD voltage is higher than Vdet2. 
An output delay time for the over-discharge 
detection is fixed internally. Through the VDD 
voltage would be going down to a lower level 
than Vdet2 if it is within a time period of the 
output delay time, VD2 would not output a 
signal for turning “OFF” of discharge control 
VD3/Excess Current Detector, Short Circuit Protector 
Both of the excess current detector and short 
  T63H0001A
TM Technology Inc. reserves the right
P. 5  
to change products or specifications without notice.  
Publication Date:MAR. 2004 
Revision:A
“OFF” of charge control Nch-MOS-FET. 
A level shifter incorporated in a buffer driver for 
the Cout pin makes the “L” of Cout pin to the 
VM pin voltage and the “H” of Cout pin is set to 
VDD voltage with CMOS buffer. 
the VDD level is within hysteresis width 
(Vdet1-Vhys1<=VDD<Vdet1) 
After detecting over-charge with the VDD 
voltage of higher than Vdet1, connecting system 
load to the battery pack makes load current 
allowable through parasitic diode of external 
charge control Nch-MOS-FET. The Cout level 
would be “H” when the VDD level is coming 
down to a level below the Vdet1 by continuous 
drawing of load current. 
pack. When the VDD voltage stays under 
over-discharge detector threshold Vdet2 charge 
current can flow through parasitic diode of 
external control Nch-MOS-FET, then after the 
VDD voltages comes up to a value larger than 
Vdet2 discharging process would be advanced 
through “ON” state discharge control 
Nch-MOS-FET. Connecting a charger to the 
battery pack makes the Dout level being “H” 
instantaneously when the 
Nch-MOS-FET. 
After detection of an over-discharge by VD2, 
supply current would be reduced to 0.3uA TYP. 
At VDD=2V and into standby, only the charger 
detector is operating. 
The output type of Dout pin is CMOS having 
“H” level of VDD and “L” level of VSS. 
circuit protector can work when both control