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參數(shù)資料
| 型號(hào)： | T555200-PAE |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PXMA |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 1154K |
| 代理商： | T555200-PAE |
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11
4697B–RFID–06/06
T5552
3.5.3
Programming
When the bit decoder and controller detect a valid data stream, the T5552 will start an erase and
programming cycle if a data write command was decoded (see Figure 3-9).
During the erase and programming cycle, downlink damping is turned off. The programming
cycle includes a data verification read to check the integrity of the data. When EEPROM pro-
gramming and verification have been finished successfully, the T5552 enters uplink mode,
transmitting the block just programmed.
The typical programming time is
≈ 18 ms.
4.
Error Handling
Several error conditions are detected by the T5552 to ensure that only valid information is pro-
grammed into the EEPROM.
4.1
Errors During EEPROM Programming
There are two types of errors which will lead to dedicated actions.
Verification error
If one of the data verification cycles fails, the T5552 will inhibit modulation and will not return
to the uplink mode. This “modulation defeat” state is terminated by re-entering the downlink
mode with a start gap.
Block write protection
If the lock bit of the addressed block is set, programming is disabled. In this case, the
programming cycle is not initiated and the T5552 reverts to uplink mode, transmitting the
currently addressed (and unmodified) block continuously.
4.2
Errors During Data Transmission
The following errors are detected by the decoder:
Bit error
Wrong number of field clocks between two gaps (i.e. not a valid “0” or “1” pulse stream).
Frame error
The number of data bits received is incorrect:
– Valid bit count for 3-bit address write is 38 bits
– Valid bit count for 5-bit address write is 40 bits
– 7 bits for a direct access command
If any of these conditions is detected, the T5552 enters uplink mode starting with block 1.
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