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參數(shù)資料
| 型號(hào)： | T555200-PAE |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PXMA |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 1154K |
| 代理商： | T555200-PAE |
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4697B–RFID–06/06
T5552
3.5
Downlink Operation
Data is transmitted from the base station by amplitude modulation of the field (m = 1), using a
series of so called gaps. With the exception of the initial synchronization gap (start gap), all field
gaps have the same duration, the logical data being encoded in the length of the unmodulated
phases (see Figure 3-5).
A valid data stream is always preceded by a start gap which is approximately twice as long as a
normal field gap. Detection of this first gap causes the T5552 to switch immediately to downlink
mode where it can receive and decode the following data stream. This stream consists of two
opcode bits, followed by (0, 3 or 5) address bits and finally (0 or 33) data bits (including the lock
bit). In downlink mode the transponder damping is permanently enabled. This loads the reso-
nant transponder coil circuit so that it comes quickly to rest when field gaps occur – thus allowing
fast gap detection.
Figure 3-5.
Entering Downlink Mode
A start gap will be accepted at any time after start-up initialization has been finished (RF field ON
plus
≈ 1 ms, start-up delay inactive) if the IC is not in downlink mode.
3.5.1
Downlink Data Coding
The duration of a field gap is typically between 80 s and 250 s. After the start gap the data bits
are transmitted by the base station whereby each bit is separated by a field gap. The bit decoder
interprets 16 to 32 internal field clocks as a logical '0' and 48 to 64 internal field clocks as a logi-
cal “1” (see Figure 3-6). Therefore, the time between two gaps is typically 24 field clocks for a “0”
and 56 field clocks for a “1”.
Whenever the bit decoder detects more than 64 field clocks, the T5552 will abort the downlink
mode. The incoming data stream is checked continuously. If any error occurs, the corresponding
error handling will be initiated.
The control logic initiates an EEPROM programming cycle if the correct number of bits had been
received (see Figure 3-7).
RF
Read mode
Receive mode
Damping ON
Damping OFF
Start gap + data '0'
Field gap + data '0'
Field gap + data '1'
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