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參數(shù)資料
| 型號： | T35L6432B-12T |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 162K |
| 代理商： | T35L6432B-12T |
TE
CH
tm
AC ELECTRICAL CHARACTERISTICS
(Note 5)
(0
°
C
≤
TA
≤
70
°
C;VCC=3.3V +0.3V/-0.165V)
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P.9
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
-9
-10
-11
-12
DESCRIPTION
SYM. MIN MAX MIN MAX MIN MAX MIN MAX UNITS
NOTES
Clock
Clock cycle time
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Output Times
Clock HIGH time
Clock LOW time
Clock to output in High-Z
OE to output valid
OE to output in Low-Z
OE to output in High-Z
Setup Times
Address
tKC
tKQ
tKQX
tKQLZ
tKH
tKL
tKQHZ
tOEQ
tOELZ
tOEHZ
tAS
tADSS
tAAS
10.5
3
3
1.8
1.8
0
1.7
15
3
3
1.9
1.9
0
2.0
2.0
2.0
15
3
3
2.0
2.0
0
2.0
15
3
3
ns
ns
ns
ns
9.0
5
5
5
10
5
5
5
11
5
5
5
12
2.0
2.0
0
ns
ns
ns
ns
ns
ns
6, 7
6, 7
9
6, 7
6, 7
8, 10
5
5
5
2.0
ns
Address Status(ADSC,ADSP)
1.7
1.7
2.0
2.0
2.0
2.0
ns
8, 10
Address Advance (ADV)
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
ns
8, 10
tWS
1.7
2.0
2.0
2.0
ns
8, 10
tDS
tCES
tAH
tADSH
tAAH
1.7
1.7
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
2.0
2.0
ns
8, 10
Chip Enables(CE ,CE2,CE2)
Hold Times
Address
ns
8, 10
0.5
0.5
0.5
ns
ns
ns
8, 10
8, 10
8, 10
8, 10
Address Status(ADSC,ADSP)
Address Advance (ADV)
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
tWH
0.5
0.5
0.5
0.5
ns
tDH
tCEH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 10
8, 10
Chip Enables(CE ,CE2,CE2)
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