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參數(shù)資料
| 型號(hào)： | T35L6432B-12T |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | T35L6432B-12T |
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TE
CH
tm
TRUTH TABLE
T35L6432B
Taiwan Memory Technology, Inc. reserves the right
P.7
to change products or specifications without notice.
Publication Date: JUL. 2002
Revision: A
OPERATION
ADDRESS
USED
CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Snooze Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Note:
1. X means "don't care." H means logic HIGH. L means logic LOW.
WRITE
= L means any one
or more byte write enable signals
(
BW1
,
BW2
,
BW3
or
)
and
BWE
are LOW, or
GW
equals LOW.
WRITE
= H means all byte write signal are HIGH.
2.
BW1
= enables write to DQ1-DQ8.
BW2
= enables write to DQ9-DQ16.
BW3
= enables
write to DQ17-DQ24.
BW4
=enables write to DQ25-DQ32.
3. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge ( LOW
to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
OE
must be HIGH before the input data
required setup time plus High-Z time for
OE
and staying HIGH throughout the input data
hold time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
ADSP
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H
edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
X
High-Z
L-H
L-H High-Z
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
Q
D
Q
Q
Q
D
D
Q
Q
D
D
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