參數(shù)資料
型號(hào): T14L1024N
廠商: TM Technology, Inc.
英文描述: 2 CHAN VIDEO SPLITTER VGA
中文描述: 128K的乘八高速CMOS靜態(tài)RAM
文件頁數(shù): 5/13頁
文件大?。?/td> 87K
代理商: T14L1024N
TE
CH
tm
AC CHARACTERISTICS
(
Vcc
=3.3V
±
0.3V, Vss = 0V, Ta = 0 to 70
°
C)
(1) READ CYCLE
T14L1024N
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: APR. 2002
Revision: C
T14L1024N-10 T14L1024N-12
SYM. MIN. MAX. MIN. MAX.
t
RC
10
-
t
AA
-
10
t
ACS
-
10
t
AOE
-
6
t
CLZ*
3
-
t
OLZ*
0
-
t
CHZ*
-
5
t
OHZ*
-
5
t
OH
3
-
T14L1024N-15
MIN.
15
PARAMETER
MAX.
-
UNIT
Read Cycle Time
12
-
ns
ns
Address Access Time
-
12
-
15
Chip Enable Access Time
-
12
-
15
ns
Output Enable to Output Valid
-
7
-
7
ns
Chip Enable to Output in Low Z
3
-
3
-
ns
Output Enable to Output in Low Z
0
-
0
-
ns
Chip Disable to Output in High Z
-
6
-
7
ns
Output Disable to Output in High Z
-
6
-
7
ns
Output Hold from Address Change
3
-
3
-
ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
T14L1024N-10 T14L1024N-12
MIN. MAX. MIN.
10
-
T14L1024N-15
MIN.
15
PARAMETER
SYM.
MAX.
-
MAX.
-
UNIT
Write Cycle Time
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ*
t
OHZ*
t
OW
12
ns
ns
Chip Enable to End of Write
8
-
10
-
11
-
Address Valid to End of Write
8
-
10
-
11
-
ns
Address Setup Time
0
-
0
-
0
-
ns
Write Pulse Width
8
-
10
-
11
-
ns
Write Recovery Time
0
-
0
-
0
-
ns
Data Valid to End of Write
6
-
8
-
8
-
ns
Data Hold from End of Write
0
-
0
-
0
-
ns
Write to Output in High Z
-
5
-
6
-
6
ns
Output Disable to Output in High Z
-
5
-
6
-
7
ns
Output Active from End of Write
* These parameters are sampled but not 100% tested.
0
-
0
-
0
-
ns
相關(guān)PDF資料
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T14L1024N-10C VGA VIDEO SPLITTER 2-CHANINCLUDES CABLES
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