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參數(shù)資料
| 型號(hào)： | SYM53C140 |
| 廠商： | LSI CORP |
| 元件分類： | 其它接口 |
| 英文描述： | Ultra2 SCSI Bus Expander(Ultra2 SCSI總線擴(kuò)展器) |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP160 |
| 封裝： | 32 MM, PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 23/68頁(yè) |
| 文件大?。?/td> | 928K |
| 代理商： | SYM53C140 |
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Interface Signal Descriptions
2-9
4.
The next stage passes the signal if it is not a data clock. If SREQ or
SACK is a data clock, it delays the leading edge to improve data
output setup times. The duration is again controlled by the input
signal.
5.
The following stage is a trailing edge signal filter. When the signal
deasserts, the filter will not permit any signal bounce. The output
signal deasserts at the first deasserted edge of the input signal.
6.
The last stage develops pull-up and pull-down signals with drive and
3-state control.
7.
A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.1.7.5 Reset Control (SRST)
A_SRST and B_SRST are also passed from the source to the load bus.
This output has pull-down control for an open collector driver. These
reset signals are processed using the following steps:
1.
The input signal is blocked if it is already being driven by the
SYM53C140.
2.
The next stage is a leading edge filter. This ensures that the output
will not switch during a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3.
A parallel function ensures that bus (transmission line) recovery
occurs for a specified time after the last signal deassertion on each
signal line.
2.1.7.6 Control/Data, Input/Output, Message, and Attention Controls
(SCD, SIO, SMSG, and SATN)
A_SCD, A_SIO, A_SMSG, A_SATN, B_SCD, B_SIO, B_SMSG and
B_SATN are control signals that have the following processing steps:
1.
The input signal is blocked if it is being driven by the SYM53C140.
2.
The next stage is a leading edge filter. This ensures the output will
not switch for a specified time after the leading edge. The duration
of the input signal determines the duration of the output.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SYM53C141 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
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